HD49343NP/HNP

Preliminary

R19DS0068EJ0200 Rev.2.00

Page 9 of 22

Jul 06, 2012

Explanation of Serial Data

 PGA Gain (D4 to D13 of address 0)

Refer to the P.4 block diagram for details. A gain shifts 3 dB by voltage setup (D12 of address 4) of VRT.

PGA gain: –6dB + 0.04 dB

 N (Log linear)

(1) At VRT = 2.0 V settings (CDS input range is 1.4 Vp-p)

CDS

(CDS is –6 dB)

PGA

0.04 dB

× N

ADC

1 V

1.4 V

4095

(2) At VRT = 2.4 V settings (CDS input range is 2.0 Vp-p)

CDS

(CDS is –6 dB)

PGA

0.04 dB

× N

ADC

1.4 V

2.0 V

4095

Figure 3 Level Dia of PGA

0

128

256

384

512

640

768

896

1023

(PGA gain code)

40

Gain (dB)

30

34dB

20

10

0

–10

–6dB

31dB

–9dB

(At VRT = 2.4V)

(At VRT = 2.0V)

Figure 4 PGA Gain Characteristics

 LPF_sel (D4 to D6 of address 1)

Frequency band restrictions of a CDS input part are chosen.

LPF_sel

Sensor Frequency

0

6 MHz

1

12 MHz

2

18 MHz

3

25 MHz

4

30 MHz

5

35 MHz

6

40 MHz

7

50 MHz

Although S/N will rise if a frequency band is lowered, but opposite side amplifier

operation becomes slow and which problem with line crawl and insufficient gain

occurs. Please choose a high point from the actually used frequency.

About LFP_sel, followings are only testing guaranteed.

(1) At Low Power mode: Data = 3

(2) At Normal Power mode: Data = 6