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UPC8105GR Datasheet(PDF) 5 Page - NEC |
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UPC8105GR Datasheet(HTML) 5 Page - NEC |
5 / 16 page Data Sheet P10807EJ3V0DS00 5 µµµµPC8105GR PIN EXPLANATION PIN NO. ASSIGN- MENT SUPPLY VOL. (V) PIN VOL.(V) FUNCTION AND APPLICATION EQUIPMENT CIRCUIT 1LOin − 0 LO input for phase shifter. This input impedance is 50 Ω matched internally. 2LOin − 2.4 Bypass of LO input. This pin is grounded through internal capacitor. Open in case of single ended. 3GND 0 − 8 4I VCC/2 − Input for I signal. This in put impedance is larger than 20 k Ω. Relations between amplitude and VCC/2 bias of input signal are following. 5I VCC/2 − Input for I signal. This in put impedance is larger than 20 k Ω. VCC/2 biased DC signal should be input. 6Q VCC/2 − Input for Q signal. This in put impedance is larger than 20 k Ω. VCC/2 biased DC signal should be input. 7Q VCC/2 − Input for Q signal. This in put impedance is larger than 20 k Ω. Relations between amplitude and VCC/2 bias of input signal are following. 12 MODout − 1.5 Output from modulator. This is emitter follower output. *1: In case of that I/Q input signals are single ended. Of course, I/Q signal inputs can be used either single endedly or differentially with proper terminations. *1 VCC/2 (v) Amp. (mVp-p) ≥ 1.35 400 ≥ 1.5 600 ≥ 1.75 1000 *1 VCC/2 (v) Amp. (mVp-p) ≥ 1.35 400 ≥ 1.5 600 ≥ 1.75 1000 1 50 Ω 2 4 5 7 6 12 Connect to the ground with minimum inductance. Track length should be kept as short as possible. |
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