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ADV7189B Datasheet(PDF) 60 Page - Analog Devices |
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ADV7189B Datasheet(HTML) 60 Page - Analog Devices |
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60 / 104 page  ADV7189B Rev. B | Page 60 of 104 PIXEL PORT CONFIGURATION The ADV7189B has a very flexible pixel port that can be config- ured in a variety of formats to accommodate downstream ICs. 251H Table 79 and 252H Table 80 summarize the various functions that the ADV7189B pins can have in different modes of operation. The ordering of components, for example, Cr vs. Cb, CHA/B/C, can be changed. Refer to the 253H SWPC Swap Pixel Cr/Cb, Address 0x27[7] section. 254H Table 79 indicates the default positions for the Cr/Cb components. OF_SEL[3:0] Output Format Selection, Address 0x03[5:2] The modes in which the ADV7189B pixel port can be configured are under the control of OF_SEL[3:0]. See 255H Table 80 for details. The default LLC frequency output on the LLC1 pin is approxi- mately 27 MHz. For modes that operate with a nominal data rate of 13.5 MHz (0001, 0010), the clock frequency on the LLC1 pin stays at the higher rate of 27 MHz. For information on outputting the nominal 13.5 MHz clock on the LLC1 pin, see the 256H LLC1 Output Selection, LLC_PAD_SEL[2:0], Address 0x8F[6:4] section. SWPC Swap Pixel Cr/Cb, Address 0x27[7] This bit allows Cr and Cb samples to be swapped. When SWPC is 0 (default), no swapping is allowed. When SWPC is 1, the Cr and Cb values can be swapped. LLC1 Output Selection, LLC_PAD_SEL[2:0], Address 0x8F[6:4] The following I2C write allows the user to select between the LLC1 (nominally at 27 MHz) and LLC2 (nominally at 13.5 MHz). The LLC2 signal is useful for LLC2-compatible wide bus (16-/20-bit) output modes. See OF_SEL[3:0] for additional information. The LLC2 signal and data on the data bus are synchronized. By default, the rising edge of LLC1/LLC2 is aligned with the Y data; the falling edge occurs when the data bus holds C data. The polarity of the clock, and therefore the Y/C assignments to the clock edges, can be altered by using the Polarity LLC pin. When LLC_PAD_SEL[2:0] is 000 (default), the output is nominally 27 MHz LLC on the LLC1 pin. When LLC_PAD_SEL[2:0] is 101, the output is nominally 13.5 MHz LLC on the LLC1 pin. Table 79. P19 to P0 Output/Input Pin Mapping Data Port Pins P[19:0] Processor, Format, and Mode 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Video Out, 8-Bit, 4:2:2 YCrCb[7:0] OUT Video Out, 10-Bit, 4:2:2 YCrCb[9:0] OUT Video Out, 16-Bit, 4:2:2 Y[7:0] OUT CrCb[7:0] OUT Video Out, 20-Bit, 4:2:2 Y[9:0] OUT CrCb[9:0] OUT Table 80. Standard Definition Pixel Port Modes Pixel Port Pins P[19:0] Function P[19:10] P9[9:0] OF_SEL[3:0] Format P[19:12] P[11:10] P[9:2] P[1:0] 0000 10-Bit at LLC1 4:2:2 YCrCb[9:2] YCrCb[1:0] Three-State Three-State 0001 20-Bit at LLC2 4:2:2 Y[9:2] Y[1:0] CrCb[9:2] CrCb[1:0] 0010 16-Bit at LLC2 4:2:2 Y[7:0] Three-state CrCb[7:0] Three-state 0011 (default) 8-Bit at LLC1 4:2:2 YCrCb[7:0] Three-state Three-state Three-state 0110-1111 Reserved Reserved. Do not use. |
Similar Part No. - ADV7189B_15 |
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Similar Description - ADV7189B_15 |
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