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ADV7181 Datasheet(PDF) 12 Page - Analog Devices |
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ADV7181 Datasheet(HTML) 12 Page - Analog Devices |
12 / 104 page ADV7181 Rev. B | Page 12 of 104 Pin No. Mnemonic Type Function 21 XTAL1 O This pin should be connected to the 27 MHz crystal or left as a no connect if an external 3.3 V, 27 MHz clock oscillator source is used to clock the ADV7181. In crystal mode, the crystal must be a fundamental crystal. 29 PWRDN I A logic low on this pin places the ADV7181 in a power-down mode. Refer to the I2C Control Register Map section for more options on power-down modes for the ADV7181. 30 ELPF I The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 42. 9 SFL O Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder. 41 REFOUT O Internal Voltage Reference Output. Refer to Figure 42 for a recommended capacitor network for this pin. 42 CML O Common-Mode Level for the Internal ADCs. Refer to Figure 42 for a recommended capacitor network for this pin. 38, 39 CAPY1, CAPY2 I ADC’s Capacitor Network. Refer to Figure 42 for a recommended capacitor network for this pin. 44 CAPC2 I ADC’s Capacitor Network. Refer to Figure 42 for a recommended capacitor network for this pin. |
Similar Part No. - ADV7181_15 |
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Similar Description - ADV7181_15 |
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