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ADV7129 Datasheet(PDF) 12 Page - Analog Devices |
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ADV7129 Datasheet(HTML) 12 Page - Analog Devices |
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12 / 20 page  ADV7129 –12– REV. 0 COMMAND REGISTER 2 (CR2) (Address Register (A10–A0) = 411H) This register contains a number of control bits as shown in the diagram. CR2 is an 8-bit wide register. CR27, CR24, CR22 and CR21 are reserved and should be set to logic “0.” Figure 8 shows the various operations under the control of CR2. This register can be read from as well as written to. COMMAND REGISTER 2-BIT DESCRIPTION PLL Control (CR20) This bit resets the PLL divider when set to logic “0” and re- leases it when set to logic “1.” SYNCOUT Control (CR23) This bit is an enable for SYNCOUT. If this bit is set to logic “1,” the SENSE output becomes a pipelined version of CSYNC . Otherwise the SENSE output remains unaffected. SENSE Bit (CR25) This output bit is used to determine the absence of a CRT monitor. When CR25 is set to logic “1,” a CRT is not present. With some diagnostic code, the presence of loading on the indi- vidual RGB lines can be determined. The reference is generated by a voltage divider from the external voltage reference on the VREF pin. For the proper operation, the following levels should be applied to the comparator by the IOR, IOG and IOB outputs: DAC Low Voltage ≤ 250 mV. DAC High Voltage ≥ 450 mV. VCO Override Bit (CR26) This bit is used to override the VCO and set the PLL to the lowest frequency possible. If the external LOADIN source takes some time before it reaches its required frequency, the internal PLL can become unstable as it tries to track to a varying LOADIN signal. The VCO override bit can be set to logic level “0” and then released (set to logic level “1”) to allow the VCO to track to the input after it has stabilized. It is required to allow 200 µs before the VCO override bit is released. GAIN ERROR REGISTERS (Address Register (A10–A0) = 405H–407H) The Red, Green and Blue Gain Error Registers allow the user to compensate for any channel-to-channel variations in the video output system. They control internal resistors from each of the three DAC outputs to GND, i.e., they appear in parallel with the external termination resistor across the DAC outputs. This allows the RGB output voltages to be adjusted as the value of RINT is varied. A logic “1” on any of the control bits GR06 to GR00 switches in the appropriate resistor. A logic “0” disables or open circuits the resistor. Bit GR07 of the Gain Error Register enables or disables the Gain Error Adjust. Figure 9 shows the typical resistor values for these internal resistances versus RSET. CR27 CR26 CR25 CR24 CR23 CR22 CR21 CR20 SENSE OUTPUT 0 MONITOR PRESENT 1 MONITOR NOT PRESENT CR25 SYNCOUT CONTROL 0 IGNORE 1 DECODE CR23 RESERVED (CR27) THIS BIT SHOULD BE SET TO LOGIC “0” VCO OVERRIDE 0 VCO OVERRIDE 1 NORMAL PLL OPERATION CR26 RESERVED (CR24) THIS BIT SHOULD BE SET TO LOGIC “0” RESERVED (CR22, CR21) THESE BITS SHOULD BE SET TO LOGIC “0” PLL RESET 0 RESET PLL 1 RELEASE PLL CR20 Figure 8. Command Register 2 x x x x x x x 1 GAIN ERROR REGISTER RSET DACs R6 R5 R4 R3 R2 R1 R0 INTERNAL RESISTORS IOUT PIN RT1 RT2 GR06 R6 GR05 R5 GR04 R4 GR03 R3 GR02 R2 GR01 R1 GR00 R0 47 Ω 923 Ω 1926 Ω 3476 Ω 6979 Ω 16610 Ω 27037 Ω REGISTER (RESET = 280 Ω) (CABLE) (MONITOR) GR07 GR06 GR05 GR04 GR03 GR02 GR01 GR00 GAIN ERROR CONTROL 0 DISABLE GAIN ERROR ADJ 1 ENABLE GAIN ERROR ADJ GR07 Figure 9. Gain Error Register |
Similar Part No. - ADV7129_15 |
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Similar Description - ADV7129_15 |
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