ADV212

Rev. B | Page 7 of 44

NORMAL HOST MODE—READ OPERATION

Table 5.

Parameter

Mnemonic

Min

Typ

Max

Unit

RD to ACK, Direct Registers and FIFO Accesses

t

1

5

1.5 × JCLK + 7.02

ns

RD to ACK, Indirect Registers

t

1

10.5 JCLK2

15.5 × JCLK + 7.02

ns

Read Access Time, Direct Registers

5

1.5 × JCLK + 7.02

ns

Read Access Time, Indirect Registers

10.5 JCLK2

15.5 × JCLK + 7.02

ns

Data Hold

2

8.5

ns

CS to RD Setup

0

ns

Address Setup

2

ns

CS Hold

0

ns

Address Hold

2

ns

Read Inactive Pulse Width

2.5 JCLK2

ns

Read Active Pulse Width

2.5 JCLK2

ns

Read Cycle Time, Direct Registers

5.0 JCLK2

ns

1

Timing relationship between ACK falling transition and HDATA valid is not guaranteed. HDATA valid hold time is guaranteed with respect to RD rising transition.

A minimum of three JCLK cycles is recommended between ACK assert and RD deassert.

2

For a definition of JCLK, see Figure 32.

ADDR

HDATA

CS

RD

ACK

VALID

Figure 4. Normal Host Mode—Read Operation