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RFP12N06RLE Datasheet(PDF) 1 Page - Intersil Corporation |
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RFP12N06RLE Datasheet(HTML) 1 Page - Intersil Corporation |
1 / 6 page 6-12 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 RFD12N06RLE, RFD12N06RLESM, RFP12N06RLE 12A, 60V, 0.135 Ohm, N-Channel, Logic Level, Power MOSFETs These N-Channel logic level ESD protected power MOSFETs are manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use with logic level (5V) driving sources in applications such as programmable controllers, automotive switching, switching regulators, switching converters, motor drivers, relay drivers, and emitter switches for bipolar transistors. This performance is accomplished through a special gate oxide design which provides full rated conductance at gate biases in the 3V to 5V range, thereby facilitating true on-off power control directly from logic circuit supply voltages. Formerly developmental type TA09861. Features • 12A, 60V •rDS(ON) = 0.135Ω • Electrostatic Discharge Protected • UIS Rating Curve (Single Pulse) • Design Optimized for 5V Gate Drive • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol Packaging JEDEC TO-251AA JEDEC TO-252AA JEDEC TO-220AB Ordering Information PART NUMBER PACKAGE BRAND RFD12N06RLE TO-251AA 12N6LE RFD12N06RLESM TO-252AA 12N6LE RFP12N06RLE TO-220AB 12N06RLE NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in tape and reel, i.e., RFD12N06RLESM9A. G S D SOURCE DRAIN GATE DRAIN (FLANGE) DRAIN (FLANGE) GATE SOURCE GATE DRAIN (FLANGE) SOURCE DRAIN July 1999 File Number 2407.4 Data Sheet [ /Title (RFD1 2N06R LE, RFD12 N06RL ESM, RFP12 N06RL E) /Sub- ject (12A, 60V, 0.135 Ohm, N- Chan- nel, Logic Level, Power MOS- FETs) /Autho r () /Key- words (Inter- sil Corpo- ration, N- Chan- nel, Logic Level, Power MOS- |
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