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ADUC816 Datasheet(PDF) 7 Page - Analog Devices |
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ADUC816 Datasheet(HTML) 7 Page - Analog Devices |
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7 / 68 page  REV. 0 –7– ADuC816 Parameter ADuC816BS Unit Test Conditions/Comments POWER REQUIREMENTS (continued) Power Supply Currents Normal Mode 16, 17 DVDD Current 4 mA max DVDD = 4.75 V to 5.25 V, Core CLK = 1.57 MHz 2.1 mA max DVDD = 2.7 V to 3.6 V, Core CLK = 1.57 MHz AVDD Current 170 μA max AVDD = 5.25 V, Core CLK = 1.57 MHz DVDD Current 15 mA max DVDD = 4.75 V to 5.25 V, Core CLK = 12.58 MHz 8 mA max DVDD = 2.7 V to 3.6 V, Core CLK = 12.58 MHz AVDD Current 170 μA max AVDD = 5.25 V, Core CLK = 12.58 MHz Power Supply Currents Idle Mode 16, 17 DVDD Current 1.2 mA max DVDD = 4.75 V to 5.25 V, Core CLK = 1.57 MHz 750 μA typ DVDD = 2.7 V to 3.6 V, Core CLK = 1.57 MHz AVDD Current 140 μA typ Measured @ AVDD = 5.25 V, Core CLK = 1.57 MHz DVDD Current 2 mA typ DVDD = 4.75 V to 5.25 V, Core CLK = 12.58 MHz 1 mA typ DVDD = 2.7 V to 3.6 V, Core CLK = 12.58 MHz AVDD Current 140 μA typ Measured at AVDD = 5.25 V, Core CLK = 12.58 MHz Power Supply Currents Power-Down Mode 16, 17 Core CLK = 1.57 MHz or 12.58 MHz DVDD Current 50 μA max DVDD = 4.75 V to 5.25 V, Osc. On, TIC On 20 μA max DVDD = 2.7 V to 3.6 V, Osc. On, TIC On AVDD Current 1 μA max Measured at AVDD = 5.25 V, Osc. On or Osc. Off DVDD Current 20 μA max DVDD = 4.75 V to 5.25 V, Osc. Off 5 μA typ DVDD = 2.7 V to 3.6 V, Osc. Off Typical Additional Power Supply Currents Core CLK = 1.57 MHz, AVDD = DVDD = 5 V (AIDD and DIDD) PSM Peripheral 50 μA typ Primary ADC 1 mA typ Auxiliary ADC 500 μA typ DAC 150 μA typ Dual Current Sources 400 μA typ NOTES 1Temperature Range –40 °C to +85°C. 2These numbers are not production tested but are guaranteed by Design and/or Characterization data on production release. 3The primary ADC is factory-calibrated at 25 °C with AV DD = DVDD = 5 V yielding this full-scale error. If user power supply or temperature conditions are signifi- cantly different from these, an Internal Full-Scale Calibration will restore this error to this level. 4Gain Error Drift is a span drift. To calculate Full-Scale Error Drift, add the Offset Error Drift to the Gain Error Drift times the full-scale input. 5The auxiliary ADC is factory-calibrated at 25 °C with AV DD = DVDD = 5 V yielding this full-scale error of –2.5 LSB. A system zero-scale and full-scale calibration will remove this error altogether. 6DAC linearity and AC Specifications are calculated using: reduced code range of 48 to 4095, 0 to VREF reduced code range of 48 to 3995, 0 to VDD. 7Gain Error is a measure of the span error of the DAC. 8In general terms, the bipolar input voltage range to the primary ADC is given by Range ADC = ±(V REF 2 RN)/125, where: VREF = REFIN(+) to REFIN(–) voltage and VREF = 1.25 V when internal ADC VREF is selected. RN = decimal equivalent of RN2, RN1, RN0, e.g., V REF = 2.5 V and RN2, RN1, RN0 = 1, 1, 0 the RangeADC = ±1.28 V. In unipolar mode the effective range is 0 V to 1.28 V in our example. 91.25 V is used as the reference voltage to the ADC when internal V REF is selected via XREF0 and XREF1 bits in ADC0CON and ADC1CON respectively. 10In bipolar mode, the Auxiliary ADC can only be driven to a minimum of A GND – 30 mV as indicated by the Auxiliary ADC absolute AIN voltage limits. The bipolar range is still –VREF to +VREF; however, the negative voltage is limited to –30 mV. 11Pins configured in I2C-compatible mode or SPI mode, pins configured as digital inputs during this test. 12Pins configured in I2C-compatible mode only. 13Flash/EE Memory Reliability Characteristics apply to both the Flash/EE program memory and Flash/EE data memory. 14Endurance is qualified to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at –40 °C, +25°C and +85°C, typical endurance at 25°C is 700 Kcycles. 15Retention lifetime equivalent at junction temperature (T J) = 55 °C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV will derate with junction temperature as shown in Figure 27 in the Flash/EE Memory description section of this data sheet. 16Power Supply current consumption is measured in Normal, Idle, and Power-Down Modes under the following conditions: Normal Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop. Idle Mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0 = 1, Core Execution suspended in idle mode. Power-Down Mode: Reset = 0.4 V, All P0 pins and P1.2–P1.7 pins = 0.4 V, All other digital I/O pins are open circuit, Core Clk changed via CD bits in PLLCON, PCON.1 = 1, Core Execution suspended in power-down mode, OSC turned ON or OFF via OSC_PD bit (PLLCON.7) in PLLCON SFR. 17DV DD power supply current will typically increase by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle. Specifications subject to change without notice REV. A |
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