Datasheet

R2A20169NP/SA/SP

Page 2 of 9

R03DS0020EJ0300 Rev.3.00

Jul 25, 2013

Pin Description

Pin Arrangement

Pin No.

Pin

Name

Function

[QFN]

[TSSOP

/SOP]

15

17

DI

Serial data input terminal.

(Input serial data with a 12-bit data length.)

12

14

Do

Serial data output terminal

(Data is sequentially output from the MSB bit.)

14

16

CLK

Serial clock input terminal

(Input signal from DI terminal is input to 12-bit shift register at rise of serial clock.)

13

15

LD

Load terminal

(When High level is input to LD terminal, value in 12-bit shift register is loaded

into decoder and 8-bit latch.)

16

18

Ao1

8-bit resolution D/A converter output terminals

(After power-on, all channels are reset and DAC data 00h is output.)

17

19

Ao2

20

2

Ao3

1

3

Ao4

2

4

Ao5

3

5

Ao6

4

6

Ao7

5

7

Ao8

6

8

Ao9

7

9

Ao10

10

12

Ao11

11

13

Ao12

9

11

Vcc

Power supply terminal

18

20

GND

GND terminal

8

10

D/A converter upper reference voltage input terminal

19

1

D/A converter lower reference voltage input terminal

Outline: PRSP0020DD-B[SP]

PTSP0020JB-A [SA]

Ao3

Ao4

GND

Ao2

Ao1

DI

Ao5

Ao6

Ao7

Ao8

CLK

LD

Do

Ao12

8

1

7

6

5

4

3

2

20

14

15

16

17

18

19

15

14

13

12

1

2

3

4

R2A20169NP (Top view)

Ao4

Ao5

CLK

LD

Outline: PWQN0020KB-A [NP]

Ao6

Ao7

DI

R2A20169SP/SA (Top view)

Ao10

10

9

11

12

13

Ao11

Vcc

Ao9

5

Ao8

11

Ao12

Do