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ISL6558IR-T Datasheet(PDF) 4 Page - Intersil Corporation |
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ISL6558IR-T Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 16 page 4 FN9027.12 June 21, 2005 Functional Pin Description NOTE: Pin numbers refer to the SOIC package. Check PINOUT diagrams for QFN pin numbers. VCC (Pin 1) Supplies all the power necessary to operate the chip. The IC starts to operate when the voltage on this pin exceeds the rising POR threshold and shuts down when the voltage on this pin drops below the falling POR threshold. Connect this pin to a 5V (±5%) supply. PGOOD (Pin 2) Power good is an open drain output used to indicate the status of the output voltage. This pin is pulled low when the converter output voltage is either 10% below or 15% above the reference voltage. COMP (Pin 3) Output of the internal error amplifier. Connect this pin to the external feedback compensation network. DROOP (Pin 4) Output voltage droop or active voltage positioning is provided by connecting this pin to the FB pin. An internal current source creates the droop across an external feedback resistor, RFB. If no droop is desired, this pin MUST be left open. FB (Pin 5) The FB pin is the inverting input of the internal error amplifier. Connect this pin to the external feedback compensation network and a resistor divider from the output for proper control and protection of converter load. VSEN (Pin 6) This pin is connected through a resistor divider to the converter’s output voltage to provide remote sensing. The undervoltage and overvoltage protection comparators trigger off this input. FS/EN (Pin 7) Connecting a resistor from this pin to ground sets the internal oscillator frequency. The switching frequency, FSW, of the converter is adjustable between 80kHz and 1.5MHz. Pulling this pin to ground disables the converter and three- states the PWM outputs. GND (Pin 8) Bias and reference ground for all controller signals. PWM1 (Pin 13), PWM2 (Pin 12), PWM3 (Pin 9), PWM4 (Pin 16) The controller PWM drive signals are connected to the individual HIP660x driver PWM input pins. The number of active channels is determined by the state of PWM3 and PWM4. If PWM3 is tied to VCC, this indicates to the controller that two channel operation is desired. In this case, PWM4 should be left open or tied to VCC. Tying PWM4 to VCC indicates that three channel operation is desired. ISEN1 (Pin 14), ISEN2 (Pin 11), ISEN3 (Pin 10), ISEN4 (Pin 15) These pins are used to monitor the voltage drop across the lower MOSFETs for current feedback, output voltage droop and overcurrent protection. A resistor must be placed in series with each of these inputs and their respective PHASE node. The resistor is sized such that the current feedback is 50 µA at full load. Sense lines corresponding to inactive channels should be left open. Inactive channels are those in which the PWM pin has been tied to VCC or left open. Thermal Pad (in QFN only) In the QFN package, the pad underneath the center of the IC is a thermal substrate. The PCB “thermal land” design for this exposed die pad should include thermal vias that drop down and connect to one or more buried copper plane(s). This combination of vias for vertical heat escape and buried planes for heat spreading allows the QFN to achieve its full thermal potential. This pad should be either grounded or floating, and it should not be connected to other nodes. Refer to TB389 for design guidelines. ISL6558 |
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