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ISL6559CB-T Datasheet(PDF) 8 Page - Intersil Corporation |
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ISL6559CB-T Datasheet(HTML) 8 Page - Intersil Corporation |
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8 / 21 page  8 FN9084.8 December 29, 2004 across the RDS(ON) of the lower MOSFET while it is conducting. The resulting current into the ISEN pin is proportional to the channel current, IL. The ISEN current is then sampled and held after sufficient settling time every switching cycle. The sampled current, In, is used for channel- current balance, load-line regulation, overcurrent protection, and module current sharing. From Figure 3, the following equation for In is derived: where IL is the channel current. If RDS(ON) sensing is not desired, an independent current- sense resistor in series with the lower MOSFET source can serve as a sense element. The circuitry shown in Figure 3 represents channel n of an N-channel converter. This circuitry is repeated for each channel in the converter, but may not be active depending upon the status of the PWM3 and PWM4 pins as described in the previous section. Channel-Current Balance The sampled current, In, from each active channel is used to gauge both overall load current and the relative channel current carried in each leg of the converter. The individual sample currents are summed and divided by the number of active channels. The resulting average current, IAVG, provides a measure of the total load current demand on the converter and the appropriate level of channel current. Using Figures 3 and 4, the average current is defined as where N is the number of active channels and IOUT is the total load current. The average current is then subtracted from the individual channel sample currents. The resulting error current, IER, is then filtered before it adjusts VCOMP. The modified VCOMP signal is compared to a sawtooth ramp signal and produces a pulse width which corrects for any unbalance and drives the error current toward zero. Figure 4 illustrates Intersil’s patented current-balance method as implemented on channel-1 of a multi-phase converter. Two considerations designers face are MOSFET selection and inductor design. Both are significantly improved when channel currents track at any load level. The need for complex drive schemes for multiple MOSFETs, exotic magnetic materials, and expensive heat sinks is avoided. Resulting in a cost-effective and easy to implement solution relative to single-phase conversion. Channel-current balance insures the thermal advantage of multi-phase conversion is realized. Heat dissipation is spread over multiple channels and a greater area than single phase approaches. In some circumstances, it may be necessary to deliberately design some channel-current unbalance into the system. In a highly compact design, one or two channels may be able to cool more effectively than the other(s) due to nearby air flow or heat sinking components. The other channel(s) may have more difficulty cooling with comparatively less air flow and heat sinking. The hotter channels may also be located close to other heat-generating components tending to drive their temperature even higher. In these cases, the proper selection of the current sense resistors (RISEN in Figure 3) introduces channel current unbalance into the system. Increasing the value of RISEN in the cooler channels and decreasing it in the hotter channels moves all channels into thermal balance at the expense of current balance. Voltage Regulation The output of the error amplifier, VCOMP, is compared to the sawtooth waveform to modulate the pulse width of the PWM signals. The PWM signals control the timing of the Intersil MOSFET drivers and regulate the converter output to the specified reference voltage. Three distinct inputs to the error amplifier determine the voltage level of VCOMP. The internal and external circuitry which control voltage regulation is illustrated in Figure 5. I n I L r DS ON () R ISEN ---------------------- = (EQ. 3) FIGURE 3. INTERNAL AND EXTERNAL CURRENT-SENSING CIRCUITRY In I SEN I L r DS ON () R ISEN -------------------------- = - + ISEN(n) RISEN SAMPLE & HOLD ISL6559 INTERNAL CIRCUIT EXTERNAL CIRCUIT VIN CHANNEL N UPPER MOSFET CHANNEL N LOWER MOSFET - + I L r DS ON () IL FIGURE 4. CHANNEL-1 PWM FUNCTION AND CURRENT- BALANCE ADJUSTMENT ÷ N IAVG I4 * I3 * I2 Σ - + + - + - f(j ω) PWM1 I1 VCOMP SAWTOOTH SIGNAL IER NOTE: *CHANNELS 3 and 4 are OPTIONAL. (EQ. 4) I AVG I 1 I 2 …I N ++ N ---------------------------------- = I AVG I OUT N ------------- r DS ON () R ISEN ---------------------- = ISL6559 |
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