7

FN9127.1

December 28, 2004

NC (Pins 7, 8, 11, and 12), (Pins 6, 7, 8, 11, 13 and

15 MLFP)

No internal connection.

FB (Pin 9), (Pin 9 MLFP) and COMP (Pin 10), (Pin

10 MLFP).

FB and COMP are the available external pins of the error

amplifier. The FB pin is the inverting input of the error amplifier

and the COMP pin is the error amplifier output. These pins are

used to compensate the voltage-mode control feedback loop of

the standard synchronous rectified buck converter.

12VCC(Pin 13), (Pin 12 MLFP)

Provides bias voltage for the gate drivers.The voltage at this

pin is monitored for Power-On Reset (POR) purposes.

UGATE (Pin 14), (Pin 14 MLFP)

Connect UGATE to the upper MOSFET gate. This pin

provides the gate drive for the MOSFET.

Description

Operation Overview

The ISL6529A monitors and precisely controls two output

voltage levels. Refer to the Block Diagram, Simplified Power

System Diagram, and Typical Application Schematic on pp. 2–

3. The controller is intended for use in graphics cards or

embedded processor applications with 5V and 12V bias input

available. The IC integrates both a standard buck PWM

controller and a linear controller. The PWM controller is

The PWM controller regulates the output voltage to a level

programmed by a resistor divider. The linear controller is

designed to regulate the lower current local memory voltage

Initialization

The ISL6529A automatically initializes upon application of

input power. Special sequencing of the input supplies is not

necessary. The POR function continually monitors the input

bias supply voltage at the 5VCC and 12VCC pins. The POR

function initiates soft-start operation after these supply

voltages exceed their POR threshold voltages.

Soft-Start

The POR function initiates the digital soft-start sequence.

Both the linear regulator error amplifier and PWM error

amplifier reference inputs are forced to track a voltage level

proportional to the soft-start voltage. As the soft-start voltage

slews up, the PWM comparator regulates the output relative

to the tracked soft-start voltage, slowly charging the output

capacitor(s). Simultaneously, the linear output follows the

smooth ramp of the soft-start function into normal regulation.

Figure 1 shows the soft-start sequence of an ISL6529A

evaluation board powered by an ATX supply. Note the

uniform linear output voltage rise of the two ISL6529A output

voltages. Once the voltage on 5VCC crosses the POR

thresholds, both outputs begin their soft-start sequence. The

triangle waveform from the PWM oscillator is compared to

the rising error amplifier output voltage. As the error amplifier

voltage increases, the pulse-width on the PWM increases to

reach its steady-state duty cycle. The error amplifier

reference of the linear controller also rises relative to the

soft-start reference.

Figure 2 shows the controlled stepped output voltage rise

and associated charging current of a 390

µF polymer

capacitor. By providing many small steps of current that

effectively charge the output capacitor, the potentially large

peak current resulting from a sudden, uncontrolled voltage

rise are eliminated.

The clock for the DAC producing the 30mV steps is

approximately 18.5kHz, so there is a 18.5kHz ripple current

component that lasts for the approximate 2.8ms start-up

interval. A few clock cycles are used for initialization to insure

that soft start begins near zero volts.

FIGURE 1. ATX SUPPLY POWERING AN ISL6529A

EVALUATION BOARD

5VCC INPUT

3.3V INPUT

1.5V OUTPUT

2.4V OUTPUT

ISL6529A