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ISL6504CBZ-T Datasheet(PDF) 7 Page - Intersil Corporation |
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ISL6504CBZ-T Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 16 page 7 FN9062.2 April 13, 2004 Functional Pin Description (SOIC pinout) 3V3 (Pin 5) Connect this pin to the ATX 3.3V output. This pin provides the output current for the 1V2VID pin, and is monitored for power quality. 5VSB (Pin 16) Provide a very well de-coupled 5V bias supply for the IC to this pin by connecting it to the ATX 5VSB output. This pin provides all the chip’s bias as well as the base current for Q2 (see typical application diagram). The voltage at this pin is monitored for power-on reset (POR) purposes. GND (Pin 8) Signal ground for the IC. All voltage levels are measured with respect to this pin. S3 and S5 (Pins 6 and 7) These pins switch the IC’s operating state from active (S0, S1/S2) to S3 and S4/S5 sleep states. These are digital inputs featuring internal 50k Ω (typical) resistor pull-ups to 5VSB. Internal circuitry de-glitches these pins for disturbances lasting as long as 2 µs (typically). Additional circuitry blocks any illegal state transitions (such as S3 to S4/S5 or vice versa). Respectively, connect S3 and S5 to the computer system’s SLP_S3 and SLP_S5 signals. FAULT (Pin 9) In case of an undervoltage on any of the controlled outputs, on any of the monitored ATX voltages, or in case of an overtemperature event, this pin is used to report the fault condition by being pulled to 5VSB. Connect a 1k Ω resistor from this pin to GND. SS (Pin 13) Connect this pin to a small ceramic capacitor (no less than 5nF; 0.1 µF recommended). The internal soft-start (SS) current source along with the external capacitor creates a voltage ramp used to control the ramp-up of the output voltages. Pulling this pin low with an open-drain device shuts down all the outputs as well as force the FAULT pin low. The CSS capacitor is also used to provide a controlled voltage slew rate during active-to-sleep transitions on the 3.3VDUAL/3.3VSB output. 3V3DL (Pin 3) Connect this pin to the 3.3V dual/stand-by output (VOUT3). In sleep states, the voltage at this pin is regulated to 3.3V; in active states, ATX 3.3V output is delivered to this node through a fully-on N-MOS transistor. During all operating states, this pin is monitored for undervoltage events. This pin provides all the output current delivered by the 1V5SB pin. 3V3DLSB (Pin 2) Connect this pin to the base of a suitable NPN transistor. In sleep state, this transistor is used to regulate the voltage at the 3V3DL pin to 3.3V. DLA (Pin 10) This pin is an open-collector output. Connect a 1k Ω resistor from this pin to the ATX 12V output. This resistor is used to pull the gates of suitable N-MOSFETs to 12V, which in active state, switch in the ATX 3.3V and 5V outputs into the 3.3VDUAL/3.3VSB and 5VDUAL outputs, respectively. 5VDL (Pin 12) Connect this pin to the 5VDUAL output (VOUT4). In either operating state (when on), the voltage at this pin is provided through a fully-on MOS transistor. This pin is also monitored for undervoltage events. 5VDLSB (Pin 11) Connect this pin to the gate of a suitable P-MOSFET or bipolar PNP. ISL6504: In S3 sleep state, this transistor is switched on, connecting the ATX 5VSB output to the 5VDUAL regulator output. ISL6504A: In S3 and S4/S5 sleep state, this transistor is switched on, connecting the ATX 5VSB output to the 5VDUAL regulator output. 1V5SB (Pin 1) This pin is the output of the internal 1.5V regulator (VOUT1). This internal regulator operates for as long as 5VSB is applied to the IC and draws its output current from the 3V3DL pin. This pin is monitored for undervoltage events. 1V2VID (Pin 4) This pin is the output of the internal 1.2V voltage identification (VID) regulator (VOUT2). This internal regulator operates only in active states (S0, S1/S2) and is shut off during any sleep state. This regulator draws its output current from the 3V3 pin. This pin is monitored for undervoltage events. VID_PG (Pin 14) This pin is the open collector output of the 1V2VID power good comparator. Connect a 10k Ω pull-up resistor from this pin to the 1V2VID output. As long as the 1V2VID output is below its UV threshold, this pin is pulled low. VID_CT (Pin 15) Connect a small capacitor from this pin to ground. The capacitor is used to delay the VID_PG reporting the 1V2VID has reached power good limits. Description Operation The ISL6504/A controls 4 output voltages (Refer to Figures 1, 2, and 3). It is designed for microprocessor computer applications with 3.3V, 5V, 5VSB, and 12V bias input from an ATX power supply. The IC is composed of three linear controllers/regulators supplying the computer system’s 1.5VSB (VOUT1), 3.3VSB and PCI slots’ 3.3VAUX power (VOUT3), the 1.2V VID circuitry power (VOUT2), a dual switch controller supplying the 5VDUAL voltage (VOUT4), as ISL6504, ISL6504A |
Similar Part No. - ISL6504CBZ-T |
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Similar Description - ISL6504CBZ-T |
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