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ISL6529 Datasheet(PDF) 10 Page - Intersil Corporation

Part # ISL6529
Description  Dual Regulator.Synchronous Rectified Buck PWM and Linear Power Controller
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL6529 Datasheet(HTML) 10 Page - Intersil Corporation

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10
FN9070.5
April 12, 2005
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
and the impedance networks ZIN and ZFB. They provide the
link between the modulator transfer function and a
controllable closed loop transfer function of VOUT/VREF. The
goal of component selection for the compensation network is
to provide a loop gain with high 0dB crossing frequency
(f0dB) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f0dB and 180
degrees.
Compensation Break Frequency Equations
Follow this procedure for selecting compensation
components by locating the poles and zeros of the
compensation network:
1. Set the loop gain (R2/R1) to provide a converter
bandwidth of one quarter of the switching frequency.
2. Place the first compensation zero, FZ1, below the output
filter double pole (~75% FLC).
3. Position the second compensation zero, FZ2, at the
output filter double pole, FLC.
4. Locate the first compensation pole, FP1, at the output
filter ESR zero, FESR.
5. Position the second compensation pole at half the
converter switching frequency, FSW.
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin; repeat if necessary.
FIGURE 6. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
VOUT
VREF
LOUT
CO
ESR
VIN
V
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
+
-
0.8V
R1
R3
R2
C3
C2
C1
COMP
VOUT
FB
ZFB
ISL6529
ZIN
COMP
DETAILED COMPENSATION COMPONENTS
PHASE
VE/A
+
-
+
+
ZFB
ZIN
OSC
F
LC
1
2
π
L
O
C
O
×
×
----------------------------------------
=
F
ESR
1
2
π ESR C
O
×
×
-----------------------------------------
=
(EQ. 5)
(EQ. 6)
F
Z1
1
2
π R
× 2C1
×
-----------------------------------
=
F
Z2
1
2
π
R1
R3
+
() C3
×
×
-------------------------------------------------------
=
F
P1
1
2
π R
2
C1
C2
×
C1
C2
+
----------------------


×
×
-------------------------------------------------------
=
F
P2
1
2
π R
× 3C3
×
-----------------------------------
=
(EQ. 10)
(EQ. 11)
(EQ. 8)
(EQ. 9)
Zeros:
Poles:
X1
-
+
INTERNAL 0.8V
REFERENCE
C4
CISS = CGS + CGD
REGULATED OUTPUT
RLOAD
1/gfs
ESR
GATE
SOURCE
DRAIN
RSAMPLE
COUTPUT
SIMPLIFIED MODEL
OF THE MOSFET
R12
AMPLIFIER
ERROR
ISL6529
DRIVE2
FB
CGD
CGS
C16
INPUT VOLTAGE
R5
R6
FIGURE 7. FIGURE A. SIMPLIFIED DIAGRAM OF THE LINEAR VOLTAGE REGULATOR
ISL6529, ISL6529A


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