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ISL6528CB Datasheet(PDF) 8 Page - Intersil Corporation |
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ISL6528CB Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 13 page 8 FN9038.3 December 28, 2004 Compensation Break Frequency Equations Follow this procedure for selecting compensation components by locating the poles and zeros of the compensation network: 1. Set the loop gain (R2/R1) to provide a converter bandwidth of one quarter of the switching frequency. 2. Place the first compensation zero, FZ1, below the output filter double pole (~75% FLC). 3. Position the second compensation zero, FZ2, at the output filter double pole, FLC. 4. Locate the first compensation pole, FP1, at the output filter ESR zero, FESR. 5. Position the second compensation pole at half the converter switching frequency, FSW. 6. Check gain against error amplifier’s open-loop gain. 7. Estimate phase margin; repeat if necessary. 8. Figure 6 shows an asymptotic plot of the DC-DC converter’s gain vs. frequency. The actual modulator gain has a high gain peak dependent on the quality factor (Q) of the output filter, which is not shown in Figure 6. Using the above procedure should yield a compensation gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45°. Include worst case component variations when determining phase margin. Application Guidelines Layout Considerations Layout is very important in high frequency switching converter design. With power devices switching efficiently at 600kHz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. Careful component layout and printed circuit board design minimizes the voltage spikes in the converters. As an example, consider the turn-off transition of the PWM MOSFET. Prior to turn-off, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is picked up by the lower Schottky diode. Any parasitic inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide traces minimizes the magnitude of voltage spikes. There are two sets of critical components in a DC-DC converter using the ISL6528. The switching components are the most critical because they switch large amounts of energy, and therefore tend to generate large amounts of noise. Next are the small signal components which connect to sensitive nodes or supply critical bypass current and signal coupling. A multi-layer printed circuit board is recommended. Figure 7 shows the connections of the critical components in the converter. Note that capacitors CIN and COUT could each represent numerous physical capacitors. Dedicate one solid layer, usually a middle layer of the PC board, for a ground plane and make all critical component ground connections through vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Keep the metal runs from the PHASE terminal to the output inductor short. The power plane should support the input and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase node. Use the remaining printed circuit layers for small signal wiring. The wiring traces from the UGATE pin to the MOSFET gate should be kept short and wide enough to easily handle the 1A of drive current. The switching components should be placed close to the ISL6528 first. Minimize the length of the connections between the input capacitors, CIN, and the power switches FZ1 1 2 π R × 2C1 × ----------------------------------- = FZ2 1 2 π R1 R3 + () C3 × × ------------------------------------------------------- = FP1 1 2 π R 2 C1 C2 × C1 C2 + ---------------------- × × ------------------------------------------------------- = FP2 1 2 π R × 3C3 × ----------------------------------- = (EQ. 10) (EQ. 11) (EQ. 8) (EQ. 9) Zeros: Poles: FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN 100 80 60 40 20 0 -20 -40 -60 FP1 FZ2 10M 1M 100K 10K 1K 100 10 OPEN LOOP ERROR AMP GAIN FZ1 FP2 FLC FESR COMPENSATION FREQUENCY (Hz) GAIN MODULATOR GAIN LOOP GAIN 20 VIN VOSC ------------------ log 20 R2 R1 --------- log ISL6528 |
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