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ISL6504CRZ Datasheet(PDF) 9 Page - Intersil Corporation

Part # ISL6504CRZ
Description  Multiple Linear Power Controller with ACPI Control Interface
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL6504CRZ Datasheet(HTML) 9 Page - Intersil Corporation

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9
FN9062.2
April 13, 2004
Soft-Start into Sleep States (S3, S4/S5)
The 5VSB POR function initiates the soft-start sequence. An
internal 10
µA current source charges an external capacitor.
The error amplifiers reference inputs are clamped to a level
proportional to the SS (soft-start) pin voltage. As the SS pin
voltage slews from about 1.25V to 2.5V, the input clamp
allows a rapid and controlled output voltage rise.
Figures 7 (ISL6504) and 8 (ISL6504A) show the soft-start
sequence for the typical application start-up into a sleep
state. At time T0 5VSB (bias) is applied to the circuit. At time
T1, the 5VSB surpasses POR level. An internal fast charge
circuit quickly raises the SS capacitor voltage to
approximately 1V, then the 10
µA current source continues
the charging.
The soft-start capacitor voltage reaches approximately
1.25V at time T2, at which point the 3.3VDUAL/3.3VSB and
1.5VSB error amplifiers’ reference inputs start their
transition, resulting in the output voltages ramping up
proportionally. The ramp-up continues until time T3 when the
two voltages reach the set value. As the soft-start capacitor
voltage reaches approximately 2.75V, the undervoltage
monitoring circuit of this output is activated and the soft-start
capacitor is quickly discharged to approximately 1.25V.
Following the 3ms (typical) time-out between T3 and T4, the
soft-start capacitor commences a second ramp-up designed
to smoothly bring up the remainder of the voltages required
by the system. At time T5, voltages are within regulation
limits, and as the SS voltage reaches 2.75V, all the
remaining UV monitors are activated and the SS capacitor is
quickly discharged to 1.25V, where it remains until the next
transition. As the 1.2VVID output is only active while in an
active state, it does not come up, but rather waits until the
main ATX outputs come up within regulation limits.
Soft-Start into Active States (S0, S1)
If both S3 and S5 are logic high at the time the 5VSB is
applied, the ISL6504/A will assume active state wake-up and
keep off the required outputs until some time (typically
25ms) after the monitored main ATX output (3.3V) exceeds
the set threshold. This time-out feature is necessary in order
to ensure the main ATX outputs are stabilized. The time-out
also assures smooth transitions from sleep into active when
sleep states are being supported. 3.3VDUAL/3.3VSB and
1.5VSB outputs will come up right after bias voltage
surpasses POR level.
0V
0V
TIME
SOFT-START
(1V/DIV)
OUTPUT
(1V/DIV)
VOLTAGES
VOUT1 (1.5VSB)
VOUT4 (5VDUAL) IF S3
T1 T2
T3
T0
5VSB
(1V/DIV)
T5
T4
VOUT3 (3.3VDUAL/3.3VSB)
VOUT2
(1.2VVID)
VOUT4 (5VDUAL) if S5
FIGURE 7. SOFT-START INTERVAL IN A SLEEP
STATE; ISL6504
0V
0V
SOFT-START
(1V/DIV)
OUTPUT
(1V/DIV)
VOLTAGES
VOUT1 (1.5VSB)
VOUT4 (5VDUAL)
T1 T2
T3
T0
5VSB
(1V/DIV)
T5
T4
VOUT3 (3.3VDUAL/3.3VSB)
VOUT2
(1.2VVID)
FIGURE 8. SOFT-START INTERVAL IN A SLEEP
STATE; ISL6054A
TIME
ISL6504, ISL6504A


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