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ISL6504AEVAL1 Datasheet(PDF) 8 Page - Intersil Corporation |
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ISL6504AEVAL1 Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 16 page 8 FN9062.2 April 13, 2004 well as all the control and monitoring functions necessary for complete ACPI implementation. Initialization The ISL6504/A automatically initializes upon receipt of input power. The Power-On Reset (POR) function continually monitors the 5VSB input supply voltage, initiating 3.3VDUAL/3.3VSB and 1.5VSB soft-start operation shortly after exceeding POR threshold. Dual Outputs Operational Truth Table Table 1 describes the truth combinations pertaining to the 3.3VDUAL/SB and 5VDUAL outputs. The last two lines highlight the only difference between the ISL6504 and ISL6504A. The internal circuitry does not allow the transition from an S3 (suspend to RAM) state to an S4/S5 (suspend to disk/soft off) state or vice versa. The only ‘legal’ transitions are from an active state (S0, S1) to a sleep state (S3, S5) and vice versa. Functional Timing Diagrams Figures 4 (ISL6504), 5 (ISL6504A), and 6 are timing diagrams, detailing the power up/down sequences of all the outputs in response to the status of the sleep-state pins (S3, S5), as well as the status of the input ATX supply. Not shown in these diagrams is the deglitching feature used to protect against false sleep state tripping. Both S3 and S5 pins are protected against noise by a 2 µs filter (typically 1–4µs). This feature is useful in noisy computer environments if the control signals have to travel over significant distances. Additionally, the S3 pin features a 200 µs delay in transitioning to sleep states. Once the S3 pin goes low, an internal timer is activated. At the end of the 200 µs interval, if the S5 pin is low, the ISL6504/A switches into S5 sleep state; if the S5 pin is high, the ISL6504/A goes into S3 sleep state. TABLE 1. 5VDUAL OUTPUT (VOUT4) TRUTH TABLE S5 S3 3.3VDL/SB 5VDL COMMENTS 1 1 3.3V 5V S0/S1/S2 States (Active) 1 0 3.3V 5V S3 0 1 Note Maintains Previous State 0 0 3.3V 0V S4/S5 (ISL6504) 0 0 3.3V 5V S4/S5 (ISL6504A) NOTE: Combination Not Allowed. FIGURE 4. 5VDUAL AND 3.3VDUAL/3.3VSB TIMING DIAGRAM; ISL6504 5VSB 3.3V, 5V S3 S5 5VDLSB DLA 3V3DLSB 3V3DL 5VDL FIGURE 5. 5VDUAL AND 3.3VDUAL/3.3VSB TIMING DIAGRAM; ISL6504A 5VSB 3.3V, 5V S3 S5 5VDLSB DLA 3V3DLSB 3V3DL 5VDL FIGURE 6. 1.5VSB, AND 1.2VVID TIMING DIAGRAM 5VSB 3.3V, S3 S5 1V2VID DLA 1V5SB 5V, 12V ISL6504, ISL6504A |
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