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ISL6505EVAL1 Datasheet(PDF) 11 Page - Intersil Corporation |
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ISL6505EVAL1 Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 17 page 11 Application Guidelines Soft-Start Interval The 5VSB output of a typical ATX supply is capable of 725mA, with newer models rated for 1.0A, and even 2.0A. During power-up in a sleep state, the 5VSB ATX output needs to provide sufficient current to charge up all the applicable output capacitors and, simultaneously, provide some amount of current to the output loads. Drawing excessive amounts of current from the 5VSB output of the ATX can lead to voltage collapse and induce a pattern of consecutive restarts with unknown effects on the system’s behavior or health. The built-in soft-start circuitry allows tight control of the slew- up speed of the output voltages controlled by the ISL6505, thus enabling power-ups free of supply drop-off events. Since the outputs are ramped up in a linear fashion, the current dedicated to charging the output capacitors can be calculated with the following formula: where ISS - soft-start current (typically 10µA) CSS - soft-start capacitor VBG - bandgap voltage (typically 1.26V) Σ(C OUT x VOUT) - sum of the products between the capacitance and the voltage of an output (total charge delivered to all outputs) Due to the various system timing events and their interaction, it is recommended that the soft-start interval not be set to exceed 30ms. For most applications, a 0.1 µF capacitor is recommended. Shutdown In case of a FAULT condition that might endanger the computer system, or at any other time, all the ISL6505 outputs can be shut down by pulling the SS pin below the specified shutdown level (typically 0.8V) with an open drain or open collector device capable of sinking a minimum of 2mA. Pulling the SS pin low effectively shuts down all the pass elements. Upon release of the SS pin, the ISL6505 undergoes a new soft-start cycle and resumes normal operation in accordance to the ATX supply and control pins status. VID_PG Delay During power-up and initial soft-start, the VID_PG and VID_CT pins are held low. As the 1V2VID output exceeds its rising power-good threshold (typically 90% of its final value), the capacitor connected at the VID_CT pin starts to charge up through the internal 10 µA current source. As the voltage on this capacitor exceeds 1.25V, the open-collector VID_PG pin is released and VID POWER GOOD status is thus reported. The value of the VID_CT capacitor to be used to obtain a given VID_PG delay can be determined from the graph in Figure 10. For extended delays exceeding the range of the graph, use the following formula: , where tDELAY - desired delay time (s) C - VID_CT capacitor to obtain desired delay time (F) If no delay is needed, then a very small (pF) capacitor, or even no capacitor at all will generate a very short delay (just the pin capacitance of ~10pF should give a delay of ~1 µs). The value of the external VID_PG pull-up resistor is determined by the trade-off between the pull-down current available from the pin versus the rise time needed. In the typical power-up sequence (as described above), the VID_PG starts low (VID Power NOT Good) until the 1V2VID output reaches its power-good threshold (90%), which starts the VID_CT pin charging. When that pin reaches its trip point, the VID_PG pin open-drain pull-down device shuts off, and the external pull-up resistor (R2, as shown in Figure 13) will pull the output up to the positive supply (typically 1V2VID). This rise time is determined not by the ISL6505, but simply by the RC time constant of the pull-up resistor, and whatever capacitance is on the node, from the VID_PG output pin to whatever signals it is driving, including the pin capacitances and all of the parasitics; this may vary from one system implementation to another. The R2 value in Figure 13 (and on the ISL6505EVAL1/2 boards) is listed as 10k Ω, which may work fine in some systems. However, some of the newer systems may require a faster rise time than allowed by the 10k Ω resistor, so a lower value of resistance should be chosen. But the VID_PG pin must be able to pull down low enough against the resistor to guarantee a low logic level for whatever control I COUT I SS C SS V BG × ------------------------------ Σ C OUT V OUT × () × , = FIGURE 10. VID_PG DELAY DEPENDENCE ON VID_CT CAPACITOR 0 10 20 30 40 50 60 70 80 VID_PG DELAY (ms) 0 12 3 4 56 789 10 C t DELAY 125000 -------------------- = ISL6505 |
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