RMQSKA3636DGBA_15 datasheet(7/31 Pages) RENESAS

Part #	RMQSKA3636DGBA

Description	36-Mbit QDR??II SRAM 4-word Burst Architecture (2.0 Cycle Read latency) with ODT

Download	31 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

7 / 31 page

RMQSKA3636DGBA, RMQSKA3618DGBA

Preliminary Datasheet

R10DS0239EJ0002 Rev.0.02

Page 7 of 30

Dec. 01, 2014

Name

I/O type

Descriptions

Note

D0 to Dn

Input

Synchronous data inputs: Input data must meet setup and hold times around the

rising edges of K and /K during WRITE operations. See Pin Arrangement figures

for ball site location of individual signals.

The

×18 device uses D0 to D17. D18 to D35 should be treated as NC pin.

The

×36 device uses D0 to D35.

CQ, /CQ

Output

Synchronous echo clock outputs: The edges of these outputs are tightly matched

to the synchronous data outputs and can be used as a data valid indication.

These signals run freely and do not stop when Q tri-states.

TDO

Output

IEEE 1149.1 test output: 1.8 V I/O level.

Q0 to Qn

Output

Synchronous data outputs: Output data is synchronized to the K clock. This bus

operates in response to /R commands. See Pin Arrangement figures for ball site

location of individual signals.

The

×18 device uses Q0 to Q17. Q18 to Q35 should be treated as NC pin.

The

×36 device uses Q0 to Q35.

QVLD

Output

Valid output indicator: The Q Valid indicates valid output data. QVLD is edge

aligned with CQ and /CQ.

VDD

Supply

Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions

for range.

1

VDDQ

Supply

Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC

Characteristics and Operating Conditions for range.

1

VSS

Supply

Power supply: Ground.

1

VREF

-

HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve

system noise margin. Provides a reference voltage for the HSTL input buffers.

NC

-

No connect: These pins can be left floating or connected to 0V to VDDQ.

Notes:

1.

All power supply and ground balls must be connected for proper operation of the device.

Similar Part No. - RMQSKA3636DGBA_15

Manufacturer	Part #	Datasheet	Description
Renesas Technology Corp	RMQSKA3636DGBA	399Kb / 31P	36-Mbit QDR™ II SRAM 4-word Burst Architecture (2.0 Cycle Read latency) with ODT May 25, 2015

More results

Similar Description - RMQSKA3636DGBA_15

Manufacturer	Part #	Datasheet	Description
Renesas Technology Corp	RMQSKA3636DGBA	399Kb / 31P	36-Mbit QDR™ II SRAM 4-word Burst Architecture (2.0 Cycle Read latency) with ODT May 25, 2015
	RMQSDA3636DGBA	898Kb / 31P	36-Mbit QDR??II SRAM 4-word Burst Architecture (2.5 Cycle Read latency) with ODT
	RMQSGA3636DGBA	853Kb / 30P	36-Mbit QDR??II SRAM 4-word Burst Architecture (2.0 Cycle Read latency)
Cypress Semiconductor	CY7C1241V18	1Mb / 28P	36-Mbit QDR??II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
Renesas Technology Corp	RMQSDA3636DGBA	403Kb / 31P	36-Mbit QDR™ II SRAM 4-word Burst Architecture (2.5 Cycle Read latency) with ODT May 25, 2015
	RMQSGA3636DGBA	359Kb / 30P	36-Mbit QDR™ II SRAM 4-word Burst Architecture (2.0 Cycle Read latency) May 25, 2015
	R1QKA4436RBG	967Kb / 31P	144-Mbit QDR?줚I SRAM 4-word Burst Architecture(2.0 Cycle Read latency) with ODT
Cypress Semiconductor	CY7C2245KV18	841Kb / 28P	36-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
Renesas Technology Corp	RMQSAA3636DGBA	832Kb / 30P	36-Mbit QDR??II SRAM 4-word Burst Architecture (2.5 Cycle Read latency)
Cypress Semiconductor	CY7C1141V18	1Mb / 28P	18-Mbit QDR??II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

More results

RMQSKA3636DGBA Datasheet(PDF) 7 Page - Renesas Technology Corp

RMQSKA3636DGBA Datasheet(HTML) 7 Page - Renesas Technology Corp

Similar Part No. - RMQSKA3636DGBA_15

Similar Description - RMQSKA3636DGBA_15

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Datasheet Download

Link URL