7

Comparator to compensate for the detected “above average”

current in that channel.

Droop Compensation

In addition to control of each power channel’s output current,

the average channel current is also used to provide CORE

voltage “droop” compensation. Average full channel current

is defined as 50

amount of voltage droop required at full load current can be

programmed. The average current driven into the FB pin

direction to make the Error Amplifier “see” a higher voltage at

the inverting input, resulting in the Error Amplifier adjusting

is equal to the “droop” voltage. See the “Current Sensing and

Balancing” section for more details.

Applications and Convertor Start-Up

Each PWM power channel’s current is regulated. This

enables the PWM channels to accurately share the load

current for enhanced reliability. The HIP6601, HIP6602 or

HIP6603 MOSFET driver interfaces with the ISL6223. For

more information, see the HIP6601, HIP6602 or HIP6603

data sheets.

out of phase. Figure 2 shows the out of phase relationship

between the two PWM channels.

Power supply ripple frequency is determined by the channel

For example, if the channel frequency is set to 250kHz, the

ripple frequency is 500kHz with two channels.

The IC monitors and precisely regulates the CORE voltage

of a microprocessor. After initial start-up, the controller also

provides protection for the load and the power supply. The

following section discusses these features.

Initialization

The ISL6223 operates from a 5V power supply. Many

pin of the ISL6223. Oscillator, Sawtooth Generator, Soft-

Start and other functions are initialized during this interval.

These circuits are controlled by POR, Power-On Reset.

During this interval, the PWM outputs are driven to a three

state condition that makes these outputs essentially open.

This state results in no gate drive to the output MOSFETs.

level to insure proper internal function, the PWM outputs are

enabled and the Soft-Start sequence is initiated. If for any

POR circuit shuts the converter down and again three states

the PWM outputs.

Soft-Start

4.375V, the Soft-Start sequence is initiated. Soft-Start, by its

slow rise in CORE voltage from zero, avoids an overcurrent

condition by slowly charging the discharged output

capacitors. This voltage rise is initiated by an internal DAC

that slowly raises the reference voltage to the error amplifier

input. The voltage rise is controlled by the oscillator

frequency and the DAC within the ISL6223, therefore, the

output voltage is effectively regulated as it rises to the final

programmed CORE voltage value.

For the first 64 PWM switching cycles, the DAC output

remains inhibited and the PWM outputs remain three stated.

From the 65th cycle and for another, approximately 300

cycles the PWM output remains low, clamping the lower

output MOSFETs to ground, see Figure 3. The time

variability is due to the Error Amplifier, Sawtooth Generator

and Comparators moving into their active regions. After this

short interval, the PWM outputs are enabled and increment

the PWM pulse width from zero duty cycle to operational

pulse width, thus allowing the output voltage to slowly reach

the CORE voltage. The CORE voltage will reach its

programmed value before the 4096 cycles, but the PGOOD

output will not be initiated until the 4096th switching cycle.

320

µs, the PWM outputs are held in a three state level as

explained above. After this period and a short interval

described above, the PWM outputs are initiated and the

voltage rises in 20.16ms, for a total delay time DT of

20.48ms.

Figure 3 shows the start-up sequence as initiated by an

enabled at the falling edge of the EN switch output.

Figure 4 shows the waveforms when the regulator is

operating at 200kHz. Note that the Soft-Start duration is a

function of the Channel Frequency as explained previously.

Also note the pulses on the COMP terminal. These pulses

are the current correction signal feeding into the comparator

input (see the Block Diagram on page 2).

Figure 5 shows the regulator operating from a 12V battery

supply. In this system, the battery voltage is available before

controller IC. In this figure, note the slight rise in PGOOD as

PWM 1

PWM 2

FIGURE 2. TWO PHASE PWM OUTPUT AT 500kHz

ISL6223