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ISL6219A Datasheet(PDF) 15 Page  Intersil Corporation 

ISL6219A Datasheet(HTML) 15 Page  Intersil Corporation 
15 / 17 page 15 In Equations 18, L is the perchannel filter inductance divided by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalentseries resistance of the bulk outputfilter capacitance; and VPP is the peaktopeak sawtooth signal amplitude as described in Figure 5 and “Electrical Specifications”. Output Filter Design The output inductors and the output capacitor bank together form a lowpass filter responsible for smoothing the pulsating voltage at the phase nodes. The output filter also must provide the transient energy during the interval of time after the beginning of the transient until the regulator can fully respond. Because it has a low bandwidth compared to the switching frequency, the output filter necessarily limits the system transient response leaving the output capacitor bank to supply or sink load current while the current in the output inductors increases or decreases to meet the demand. In highspeed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. Output filter design begins with minimizing the cost of this part of the circuit. The critical load parameters in choosing the output capacitors are the maximum size of the load step, ∆I; the loadcurrent slew rate, di/dt; and the maximum allowable outputvoltage deviation under transient loading, ∆VMAX. Capacitors are characterized according to their capacitance, ESR, and ESL (equivalent series inductance). At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. The capacitors selected must have sufficiently low ESL and ESR so that the total output voltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount The filter capacitor must have sufficiently low ESL and ESR so that ∆V < ∆VMAX. Most capacitor solutions rely on a mixture of highfrequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited highfrequency performance. Minimizing the ESL of the highfrequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation. The ESR of the bulk capacitors also creates the majority of the outputvoltage ripple. As the bulk capacitors sink and source the inductor ac ripple current (see Interleaving and Equation 2), a voltage develops across the bulkcapacitor ESR equal to IPP (ESR). Thus, once the output capacitors are selected, the maximum allowable ripple voltage, VPP(MAX), determines the a lower limit on the inductance. Since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductors must be capable of assuming the entire load current before the output voltage decreases more than ∆VMAX. This places an upper limits on inductance. Equation 22 gives the upper limit on L for the cases when the trailing edge of the current transient causes a greater output voltage deviation than the leading edge. Equation 21 addresses the leading edge. Normally, the trailing edge dictates the selection of L because duty cycles are usually less than 50%. Nevertheless, both inequalities should be evaluated, and L should be selected based on the lower of the two results. In each equation, L is the perchannel inductance, C is the total output capacitance, and N is the number of active channels. Switching Frequency There are a number of variables to consider when choosing the switching frequency. There are considerable effects on the upperMOSFET loss calculation and, to a lesser extent, the lowerMOSFET loss calculation. These effects are outlined in MOSFETs, and they establish the upper limit for the switching frequency. The lower limit is established by the requirement for fast transient response and small output voltage ripple as outlined in Output Filter Design. Choose the lowest switching frequency that allows the regulator to meet the transientresponse requirements. Switching frequency is determined by the selection of the frequency setting resistor, RT (see the figure Typical Application on page 3). Figure 13 and Equation 23 are provided to assist in the selecting the correct value for RT. Input Capacitor Selection The input capacitors are responsible for sourcing the ac component of the input current flowing into the upper MOSFETs. Their rms current capacity must be sufficient to handle the ac component of the current drawn by the upper ∆V ESL () di dt  ESR () ∆I + ≈ (EQ. 19) LESR () V IN NV OUT – V OUT f SVINVPP MAX ()  ≥ (EQ. 20) L 2NCVO ∆I ()2  ∆V MAX ∆I ESR () – ≤ (EQ. 21) L 1.25 ()NC ∆I ()2  ∆V MAX ∆I ESR () – V IN V O – ≤ (EQ. 22) RT 10 11.09 1.13 fS () log – [] = (EQ. 23) ISL6219A 
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