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ISL6219A Datasheet(PDF) 14 Page - Intersil Corporation

Part No. ISL6219A
Description  Microprocessor CORE Voltage Regulator Precision Multi-Phase BUCK PWM Controller for Mobile Applications
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL6219A Datasheet(HTML) 14 Page - Intersil Corporation

 
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14
defined below, there is a separate set of equations for the
compensation components.
In Equations 17, L is the per-channel filter inductance
divided by the number of active channels; C is the sum total
of all output capacitors; ESR is the equivalent-series
resistance of the bulk output-filter capacitance; and VPP is
the peak-to-peak sawtooth signal amplitude as described in
Figure 5 and Electrical Specifications.
Once selected, the compensation values in Equations 17
assure a stable converter with reasonable transient perfor-
mance. In most cases, transient performance can be
improved by making adjustments to RC. Slowly increase the
value of RC while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
CC will not need adjustment. Keep the value of CC from
Equations 17 unless some performance issue is noted.
The optional capacitor C2, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 5). Keep
a position available for C2, and be prepared to install a high-
frequency capacitor of between 22pF and 150pF in case any
jitter problem is noted.
COMPENSATION WITHOUT LOAD-LINE REGULATION
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A type
III controller, as shown in Figure 12, provides the necessary
compensation.
The first step is to choose the desired bandwidth, f0, of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, fHF. This pole can be used for
added noise rejection or to assure adequate attenuation at
the error-amplifier high-order pole and zero frequencies. A
good general rule is to chose fHF =10 f0, but it can be higher
if desired. Choosing fHF to be lower than 10 f0 can cause
problems with too much phase shift below the system
bandwidth.
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equations 18, RFB is selected arbitrarily. The remaining
compensation components are then selected according to
Equations 18.
1
2
π LC
-------------------
f
0
>
R
C
R
FB
2
πf
0 Vpp LC
0.75V
IN
------------------------------------
=
C
C
0.75V
IN
2
πV
PPRFBf0
------------------------------------
=
Case 1:
1
2
π LC
-------------------
f
0
1
2
πC ESR
()
------------------------------
<
R
C
R
FB
V
PP
()2 f
0
2
LC
0.75 V
IN
--------------------------------------------
=
C
C
0.75 V
IN
2
π
()2 f
0
2 V
PPRFB LC
-------------------------------------------------------------
=
Case 2:
(EQ. 17)
f
0
1
2
πC ESR
()
------------------------------
>
R
C
R
FB
2
π f
0VppL
0.75 V
IN ESR
()
------------------------------------------
=
C
C
0.75V
IN ES R
() C
2
πV
PPRFBf0 L
-------------------------------------------------
=
Case 3:
FIGURE 12. COMPENSATION CIRCUIT FOR ISL6219A BASED
CONVERTER WITHOUT LOAD-LINE
REGULATION.
COMP
CC
RC
RFB
FB
VSEN
-
+
VDROOP
C2
C1
R1
R
1
R
FB
CESR
()
LC
C ESR
()
-----------------------------------------
=
C
1
LC
C ESR
()
R
FB
-----------------------------------------
=
C
2
0.75 V
IN
2
π
()2f
0fHF LCRFBVPP
-------------------------------------------------------------------
=
(EQ. 18)
R
C
V
PP

 2f
0 fHF LC
0.75 V
IN
2
π f
HF
LC 1


----------------------------------------------------------------------
=
C
C
0.75V
IN
2
πV
PPRFB
f
0 1
1
2
πf
HF LC
-----------------------------




----------------------------------------------------------------------------------
=
ISL6219A


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