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ISL6219A Datasheet(PDF) 10 Page - Intersil Corporation

Part No. ISL6219A
Description  Microprocessor CORE Voltage Regulator Precision Multi-Phase BUCK PWM Controller for Mobile Applications
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL6219A Datasheet(HTML) 10 Page - Intersil Corporation

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10
OVERVOLTAGE PROTECTION
If the ISL6219A detects output voltages above 115% of VID,
the controller will immediately commands all PWM outputs
low. This directs the Intersil drivers to turn on the lower
MOSFETs and protect the load by preventing any further
increase in output voltage. Once the output voltage falls to
the level set by the VID code, the PWM outputs enter high-
impedance mode. The Intersil drivers respond by turning off
both upper and lower MOSFETs. If the overvoltage condition
reoccurs, the ISL6219A will again command the lower
MOSFETs to turn on. The ISL6219A will continue to protect
the load in this fashion as long as the overvoltage repeats.
After detecting an overvoltage condition, the ISL6219A
terminates normal PWM operation until it is reset by one of
two methods. Either by pulling VCC below the POR falling
threshold and restoring it above the POR rising threshold or
cycling FS/EN.
Under-Voltage
The VSEN pin also detects when the CORE voltage drops
below the VID programmed under-voltage falling threshold.
This causes PGOOD to go low, but has no other effect on
operation and is not latched.
LOAD-LINE REGULATION
In applications with high transient current slew rates, the
lowest-cost solution for maintaining regulation often requires
some kind of controlled output impedance. A current
proportional to the average current of all active channels is
steered into the inverting input of the error amplifier. There is
no DC return path connected to the FB pin except for the
feedback resistor, RFB. Therefore, the average current,
IAVG, produces a voltage drop across the feedback resistor,
RFB, proportional to the output current. In Figure 7, the
steady-state value of VDROOP is simply
In the case that each channel uses the same value for RISEN to
sense channel current, a more complete expression for
VDROOP can be determined from the expression for IAVG as it
is derived from Figures 4 and 5.
ENABLE AND DISABLE
Three separate input conditions must be met before the
ISL6219A is released from shut-down mode. The PWM
outputs are held in a high-impedance state to assure the
drivers remain off during shut-down.
The internal power-on reset circuit (POR) prevents the
ISL6219A from starting before the bias voltage at VCC
reaches the POR-rising threshold as defined in Electrical
Specifications. The rising threshold is high enough to
guarantee that all parts of the ISL6219A can perform their
functions properly. There is enough hysteresis in the POR-
falling threshold to prevent nuisance tripping.
The frequency select/enable input (FS/EN) has a 1V threshold
which must be exceeded before the internal oscillator begins
running. An external enable signal should be used to control the
gate of an external MOSFET tied to the FS/EN pin, see Figure
8. This MOSFET must pull FS/EN below the 1V threshold to
disable the controller. When enabling the controller, this
10
100
1.350
10
011
1.375
10
010
1.400
10
001
1.425
10
000
1.450
01
111
1.475
01
110
1.500
01
101
1.525
01
100
1.550
01
011
1.575
01
010
1.600
01
001
1.625
01
000
1.650
00
111
1.675
00
110
1.700
00
101
1.725
00
100
1.750
00
011
1.775
00
010
1.800
00
001
1.825
00
000
1.850
TABLE 1. VOLTAGE IDENTIFICATION CODES (Continued)
VID4
VID3
VID2
VID1
VID0
VDAC
V
DROOP
I
AVG RFB
=
(EQ. 3)
I
AVG
I
OUT
N
-------------
r
DS ON
()
R
ISEN
----------------------
=
V
DROOP
I
OUT
N
-------------
r
DS ON
()
R
ISEN
---------------------- R
FB
=
(EQ. 4)
FIGURE 8. EXTERNAL ENABLE SIGNAL CIRCUIT
EXTERNAL CIRCUIT
FS/EN
+
-
1.23V
-
+
VCC
S1
ENABLE
SIGNAL
ISL6219A


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