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ISL6219A Datasheet(PDF) 9 Page - Intersil Corporation

Part No. ISL6219A
Description  Microprocessor CORE Voltage Regulator Precision Multi-Phase BUCK PWM Controller for Mobile Applications
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL6219A Datasheet(HTML) 9 Page - Intersil Corporation

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9
to cool more effectively than the other(s) due to nearby air
flow or heat sinking components. The other channel(s) may
have more difficulty cooling with comparatively less air flow
and heat sinking. The hotter channels may also be located
close to other heat-generating components tending to drive
their temperature even higher. In these cases, a proper
selection of the current sense resistors (RISEN in Figure 4)
introduces channel current unbalance into the system.
Increasing the value of RISEN in the cooler channels and
decreasing it in the hotter channels moves all channels into
thermal balance at the expense of current balance.
OVERCURRENT PROTECTION
The average current, IAVG in Figure 5, is continually
compared with a constant 75
µA reference current. If the
average current at any time exceeds the reference current,
the comparator triggers the converter to shut down. All PWM
signals are placed in a high-impedance state which signals
the drivers to turn off both upper and lower MOSFETs. The
system remains in this state while the controller counts 2048
phase-clock cycles.
This is followed by a soft-start attempt (see Soft-Start). If the
soft-start attempt is successful, operation will continue as
normal. Should the soft-start attempt fail, the ISL6219A
repeats the 2048-cycle wait period and follows with another
soft-start attempt. This hiccup mode of operation continues
indefinitely as shown in Figure 6 as long as the controller is
enabled or until the overcurrent condition resolves.
VOLTAGE REGULATION
The ISL6219A uses a digital to analog converter (DAC) to
generate a reference voltage based on the logic signals at
pins VID4 to VID0. The DAC decodes the a 5-bit logic signal
(VID) into one of the discrete voltages shown in Table 1. Each
VID input offers a 20
µA pull up to 2.5V for use with open-drain
outputs. External pull-up resistors or active-high output
stages can augment the pull-up current sources, but a slight
accuracy error can occur if they are pulled above 2.9V.
The integrating compensation network shown in Figure 7
assures that the steady-state error in the output voltage is
limited to the error in the reference voltage (output of the
DAC) plus offset errors in the error amplifier. Intersil specifies
the guaranteed tolerance of the ISL6219A to include all vari-
ations in the amplifiers and reference so that the output volt-
age remains within the specified system tolerance.
FIGURE 5. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
÷ N
IAVG
I3
I2
Σ
-
+
+
-
+
-
f(j
ω)
PWM1
I1
VCOMP
SAWTOOTH SIGNAL
IER
TABLE 1. VOLTAGE IDENTIFICATION CODES
VID4
VID3
VID2
VID1
VID0
VDAC
11
11
1
Off
11
11
0
1.100
11
10
1
1.125
11
10
0
1.150
11
01
1
1.175
11
01
0
1.200
11
00
1
1.225
11
00
0
1.250
10
11
1
1.275
10
11
0
1.300
10
10
1
1.325
0A
0V
5ms/DIV
OUTPUT VOLTAGE,
OUTPUT CURRENT, 20A/DIV
FIGURE 6. OVERCURRENT BEHAVIOR IN HICCUP MODE
500mV/DIV
FIGURE 7. OUTPUT-VOLTAGE AND LOAD-LINE
REGULATION
-
+
IAVG
REFERENCE
EXTERNAL CIRCUIT
ISL6219A INTERNAL CIRCUIT
COMP
CC
RC
RFB
FB
VSEN
-
+
VDROOP
ERROR AMPLIFIER
VOUT
VOLTAGE(VDAC)
VCOMP
ISL6219A


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