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ISL6219A Datasheet(PDF) 8 Page - Intersil Corporation

Part No. ISL6219A
Description  Microprocessor CORE Voltage Regulator Precision Multi-Phase BUCK PWM Controller for Mobile Applications
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Maker  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
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ISL6219A Datasheet(HTML) 8 Page - Intersil Corporation

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8
must use an input capacitor bank with twice the rms current
capacity as the equivalent three-phase converter.
Figures 14 and 15 in the section entitled Input Capacitor
Selection can be used to determine the input-capacitor rms
current based on load current, duty cycle, and the number of
active channels. They are provided as aids in determining
the optimal input capacitor solution. Figure 16 shows the
single phase input-capacitor rms current for comparisson.
PWM OPERATION
The number of active channels selected determines the
timing for each channel. By default, the timing mode for the
ISL6219A is 3-phase. The designer can select 2-phase
timing by connecting PWM3 to VCC.
One switching cycle for the ISL6219A is defined as the time
between PWM1 pulse termination signals (the internal signal
that initiates a falling edge on PWM1). The cycle time is the
inverse of the switching frequency selected by the resistor
connected between the FS/EN pin and ground (see
Switching Frequency). Each cycle begins when a clock
signal commands the channel-1 PWM output to go low. This
signals the channel-1 MOSFET driver to turn off the
channel-1 upper MOSFET and turn on the channel-1
synchronous MOSFET. If two-channel operation is selected,
the PWM2 pulse terminates 1/2 of a cycle later. If three
channels are selected the PWM2 pulse terminates 1/3 of a
cycle after PWM1, and the PWM3 output will follow after
another 1/3 of a cycle.
Once a channel’s PWM pulse terminates, it remains low for
a minimum of 1/4 cycle. This forced off time is required to
assure an accurate current sample as described in Current
Sensing. Following the 1/4-cycle forced off time, the
controller enables the PWM output. Once enabled, the PWM
output transitions high when the sawtooth signal crosses the
adjusted error-amplifier output signal, VCOMP as illustrated
in Figures 1 and 5. This is the signal for the MOSFET driver
to turn off the synchronous MOSFET and turn on the upper
MOSFET. The output will remain high until the clock signals
the beginning of the next cycle by commanding the PWM
pulse to terminate.
CURRENT SENSING
Intersil multi-phase controllers sense current by sampling the
voltage across the lower MOSFET during its conduction
interval. MOSFET rDS(ON) sensing is a no-added-cost
method to sense current for load-line regulation, channel-
current balance, module current sharing, and overcurrent
protection. If desired, an independent current-sense resistor
in series with the lower-MOSFET source can serve as a
sense element in place of the MOSFET rDS(ON).
The ISEN input for each channel uses a ground-referenced
amplifier to reproduce a signal proportional to the channel
current (Figure 4). After sufficient settling time, the sensed
current is sampled, and the sample is used for current
balance, load-line regulation and overcurrent protection. The
ISL6219A samples channel current once each cycle. Figure
4 shows how the sampled current, In, is created from the
channel current IL. The circuitry in Figure 4 represents the
current measurement and sampling circuitry for channel n in
an N-channel converter. This circuitry is repeated for each
channel in the converter but will not be active in unused
channels.
CHANNEL-CURRENT BALANCE
Another benefit of multi-phase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this, the
designer avoids the complexity of driving multiple parallel
MOSFETs and the expense of using expensive heat sinks
and exotic magnetic materials.
In order to fully realize the thermal advantage, it is important
that each channel in a multi-phase converter be controlled to
deliver about the same current at any load level. Intersil
multi-phase controllers guarantee current balance by
comparing each channel’s current to the average current
delivered by all channels and making an appropriate
adjustment to each channel’s pulse width based on the
error. Intersil’s patented current-balance method is
illustrated in Figure 5 where the average of the 2 or 3
sampled channel currents combines with the channel 1
sample, I1, to create an error signal IER. The filtered error
signal modifies the pulse width commanded by VCOMP to
correct any unbalance and force IER toward zero.
In some circumstances, it may be necessary to deliberately
design some channel-current unbalance into the system. In
a highly compact design, one or two channels may be able
FIGURE 4. INTERNAL AND EXTERNAL CURRENT-SENSING
CIRCUITRY
In
I
SEN
I
L
r
DS ON
()
R
ISEN
--------------------------
=
-
+
ISEN(n)
RISEN
SAMPLE
&
HOLD
ISL6219A INTERNAL CIRCUIT
EXTERNAL CIRCUIT
VIN
CHANNEL N
UPPER MOSFET
CHANNEL N
LOWER MOSFET
-
+
I
L
r
DS ON
()
IL
ISL6219A


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