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ISL6141CBZA Datasheet(PDF) 2 Page - Intersil Corporation |
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ISL6141CBZA Datasheet(HTML) 2 Page - Intersil Corporation |
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2 / 19 page  2 Ordering Information PART NO. TEMP. RANGE (oC) PACKAGE PKG. DWG. # ISL6141CB 0 to 70 8 Lead SOIC M8.15 ISL6141CBZA (See Note) 0 to 70 8 Lead SOIC (Pb-free) M8.15 ISL6151CB 0 to 70 8 Lead SOIC M8.15 ISL6151CBZA (See Note) 0 to 70 8 Lead SOIC (Pb-free) M8.15 ISL6141IB -40 to 85 8 Lead SOIC M8.15 ISL6141IBZA (See Note) -40 to 85 8 Lead SOIC (Pb-free) M8.15 ISL6151IB -40 to 85 8 Lead SOIC M8.15 ISL6151IBZA (See Note) -40 to 85 8 Lead SOIC (Pb-free) M8.15 *Add “-T” suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. Ordering Information (Continued) PART NO. TEMP. RANGE (oC) PACKAGE PKG. DWG. # C1 Q1 R2 R1 CL RL -48V IN -48V OUT LOAD C2 R3 + - +- VEE 1.255V + - +- VEE 50mV + - + - VEE 1.255V + - +- VEE 11.1V + - VEE 210mV + - +- VEE 1.265V + - +- VEE 1.3V R4 R5 R6 GND GND LOGIC TIMING GATE DRIVE REGULATOR, REFERENCES PWRGD LATCH LOGIC UV OV VEE SENSE VDD PWRGD GATE DRAIN UVLO UV OV CURRENT LIMIT HARD GATE GATE 13V 600 µs TIMER PWRGD FIGURE 1. BLOCK DIAGRAM FAULT (ISL6141) (ISL6151) PWRGD OUTPUT DRIVE REGULATOR VEE + - ISL6141, ISL6151 |
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