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R1QKA4418RBG-25IB0 Datasheet(PDF) 6 Page - Renesas Technology Corp

Part # R1QKA4418RBG-25IB0
Description  144-Mbit QDR?줚I SRAM 4-word Burst Architecture(2.0 Cycle Read latency) with ODT
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R1QKA4418RBG-25IB0 Datasheet(HTML) 6 Page - Renesas Technology Corp

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R1QKA4436RBG,R1QKA4418RBG
Datasheet
R10DS0138EJ0202 Rev.2.02
Page 6 of 30
Aug 01, 2014
Pin Descriptions
Name
I/O type
Descriptions
Note
SA
Input
Synchronous address inputs: These inputs are registered and must meet the setup
and hold times around the rising edge of K (read and write address). These inputs
are ignored when device is deselected.
/R
Input
Synchronous read: When low, this input causes the address inputs to be registered
and a READ cycle to be initiated. This input must meet setup and hold times around
the rising edge of K, and is ignored on the subsequent rising edge of K.
/W
Input
Synchronous write: When low, this input causes the address inputs to be registered
and a WRITE cycle to be initiated. This input must meet setup and hold times around
the rising edge of K, and is ignored on the subsequent rising edge of K.
/BWx
Input
Synchronous byte writes: When low, these inputs cause their respective byte to be
registered and written during WRITE cycles. These signals are sampled on the same
edge as the corresponding data and must meet setup and hold times around the
rising edges of K and /K for each of the two rising edges comprising the WRITE cycle.
See Byte Write Truth Table for signal to data relationship.
K, /K
Input
Input clock: This input clock pair registers address and control inputs on the rising
edge of K, and registers data on the rising edge of K and the rising edge of /K. /K is
ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and
hold times around the clock rising edges. These balls cannot remain VREF level.
/DOFF
Input
PLL disable: When low, this input causes the PLL to be bypassed for stable, low
frequency operation.
TMS
TDI
Input
IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left unconnected if the
JTAG function is not used in the circuit.
TCK
Input
IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if the JTAG
function is not used in the circuit.
ZQ
Input
Output impedance matching input: This input is used to tune the device outputs to
the system data bus impedance. Q and CQ output impedance are set to 0.2
× RQ,
where RQ is a resistor from this ball to ground. This ball can be connected directly to
VDDQ, which enables the minimum impedance mode. This ball cannot be connected
directly to VSS or left unconnected.
The ODT termination values tracks the value of RQ. The ODT range is selected by
ODT control input.
ODT
Input
ODT control: When low;
Low range mode is selected. The impedance range is between 52
Ω and 105 Ω
(Thevenin equivalent), which follows 0.3
× RQ for 175 Ω ≤ RQ ≤ 350 Ω.
ODT control:When high;
High range mode is selected. The impedance range is between 105
Ω and 150 Ω
(Thevenin equivalent), which follows 0.6
× RQ for 175 Ω ≤ RQ ≤ 250 Ω.
ODT control:When floating;
High range mode is selected.


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