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R1QAA4418RBG-19IB0 Datasheet(PDF) 7 Page - Renesas Technology Corp |
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R1QAA4418RBG-19IB0 Datasheet(HTML) 7 Page - Renesas Technology Corp |
7 / 30 page R1QAA4436RBG,R1QAA4418RBG Datasheet R10DS0137EJ0202 Rev.2.02 Page 7 of 29 Apr 25, 2014 Name I/O type Descriptions Note D0 to Dn Input Synchronous data inputs: Input data must meet setup and hold times around the rising edges of K and /K during WRITE operations. See Pin Arrangement figures for ball site location of individual signals. The ×18 device uses D0 to D17. D18 to D35 should be treated as NC pin. The ×36 device uses D0 to D35. CQ, /CQ Output Synchronous echo clock outputs: The edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q tri-states. TDO Output IEEE 1149.1 test output: 1.8 V I/O level. Q0 to Qn Output Synchronous data outputs: Output data is synchronized to the K clock. This bus operates in response to /R commands. See Pin Arrangement figures for ball site location of individual signals. The ×18 device uses Q0 to Q17. Q18 to Q35 should be treated as NC pin. The ×36 device uses Q0 to Q35. QVLD Output Valid output indicator: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and /CQ. VDD Supply Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range. 1 VDDQ Supply Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and Operating Conditions for range. 1 VSS Supply Power supply: Ground. 1 VREF - HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise margin. Provides a reference voltage for the HSTL input buffers. NC - No connect: These pins can be left floating or connected to 0V to VDDQ. Notes: 1. All power supply and ground balls must be connected for proper operation of the device. |
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Similar Description - R1QAA4418RBG-19IB0 |
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