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ISL5239KIZ Datasheet(PDF) 6 Page - Intersil Corporation |
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ISL5239KIZ Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 31 page 6 Functional Description The ISL5239 is a full-featured digital pre-distortion part featuring a high-performance lookup-table based pre- distortion (PD) processing unit. It includes an interpolator for upsampling and supports all varieties of upconversion architectures with a programmable correction filter for equalization including both sin(x)/x correction and removal of frequency response imbalance between quadrature paths. It also features gain, phase, and offset compensation for direct upconversion, digital IF output for heterodyning, and input/output capture memories with internal/external triggering capabilities to facilitate closedloop feedback processing. System implementation is typically as shown in Figure 1. Although the power detect feedback is shown with one Analog to Digital Converter (ADC), coherently demodulated feedback signalsLO configurations with 1 or 2 ADC’s are also supported. The block diagram on page 1 shows the internal functional units within the ISL5239. In the following sections each functional unit is described. The operation of the ISL5239 is controlled by the register map listed in Table 3. Detailed descriptions for each control/status register are given in Tables 4 through 48. The control/status registers are referred to in the discussion below. Input Formatter and Interpolator (IFIP) The Input Formatter and Interpolator interfaces to the data source to provide for parallel data input via the IIN<17:0>, QIN<17:0> busses, or serial input via the IIN<17:0> input bus. In parallel input mode, both 18-bit input busses are used to allow for parallel I and Q sample loading. In serial mode, the data is input via the IIN<17:0> bus only, as the I sample followed by the Q sample with the ISTRB input asserted with each I sample. In this mode, the QIN<17:0> bus is not utilized. The input data format is selectable as either two’s complement or offset binary. The Interpolator function is necessary because pre- distorting a signal results in a much wider bandwidth signal (typically 5x to 7x wider). The Input Formatter and Interpolator is depicted in Figure 2. Three interpolation rates (x2, x4, and x8) are supported by the cascade of three Half-Band (HB) Filters. The ISL5239 includes an on-chip clock divider to facilitate input clocking. The clock divider generates the CLKOUT signal which is used to clock data from the input signal source. Typical input sources include the ISL5217 quad programmable upconverter, which is designed to operate seamlessly with the ISL5239. The interpolation factor is selectable in control word 0x02, bits 6:4 as x1, x2, x4, and x8. The x1 mode bypasses all three half-band filters. The x2 mode utilized HB1 and bypasses HB2 and HB3. The x4 mode utilized HB1 and HB2 and bypasses HB3. Finally, the x8 mode utilizes all three HBFs. Saturation status bits are provided for each of the three HBFs in the status register 0x03. Input data rates up to the CLK rate are supported, based on the requirement CLK >= Fs * IP, where Fs is the input rate of the incoming data and IP is the interpolation factor selected in control word 0x02. Each half-band filter performs a x2 interpolation by inserting one zero between each input data sample, causing the sampling frequency to double. The resulting zero-stuffed data is then low pass filtered to reject the upsampling image. The half-band filter frequency responses are as shown in Figure 3. FIGURE 1. SYSTEM OVERVIEW FIGURE 3. x2, HB1 ENABLED FREQUENCY RESPONSE FIGURE 2. INPUT FORMATTER AND INTERPOLATOR BLOCK DIAGRAM QIN<17:0> IIN<17:0> HALF FILTER 1 BAND HALF FILTER 2 BAND HALF FILTER 3 BAND 20 / 20 / 18 / 20 / I Q BYPASS BYPASS BYPASS 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -140 -120 -100 -80 -60 -40 -20 0 NORMALIZED FREQUENCY (NYQUIST=1) HALFBAND FILTER 1 RESPONSE ISL5239 |
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