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EN25S20A Datasheet(PDF) 9 Page - Eon Silicon Solution Inc.

Part No. EN25S20A
Description  2 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector
Download  65 Pages
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Maker  EON [Eon Silicon Solution Inc.]
Homepage  http://www.essi.com.tw
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EN25S20A Datasheet(HTML) 9 Page - Eon Silicon Solution Inc.

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This Data Sheet may be revised by subsequent versions
©2014 Eon Silicon Solution, Inc.,
www.eonssi.com
or modifications due to changes in technical specifications.
9
EN25S20A
Rev. A, Issue Date: 2014/01/16
Table 3. Protected Area Sizes Sector Organization
Status Register Content
Memory Content
BP3
Bit
BP2
Bit
BP1
Bit
BP0
Bit
Protect Areas
Addresses
Density(KB)
Portion
0
0
0
0
None
None
None
None
0
0
0
1
Block 3
030000h-03FFFFh
64KB
Upper 1/4
0
0
1
0
Block 2 to 3
020000h-03FFFFh
128KB
Upper 2/4
0
0
1
1
Block 1 to 3
010000h-03FFFFh
192KB
Upper 3/4
0
1
0
0
All
000000h-03FFFFh
256KB
All
0
1
0
1
All
000000h-03FFFFh
256KB
All
0
1
1
0
All
000000h-03FFFFh
256KB
All
0
1
1
1
All
000000h-03FFFFh
256KB
All
1
0
0
0
None
None
None
None
1
0
0
1
Block 0
000000h-00FFFFh
64KB
Lower 1/4
1
0
1
0
Block 0 to 1
000000h-01FFFFh
128KB
Lower 2/4
1
0
1
1
Block 0 to 2
000000h-03FFFFh
192KB
Lower 3/4
1
1
0
0
All
000000h-03FFFFh
256KB
All
1
1
0
1
All
000000h-03FFFFh
256KB
All
1
1
1
0
All
000000h-03FFFFh
256KB
All
1
1
1
1
All
000000h-03FFFFh
256KB
All
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial
Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is
driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first,
on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).
The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by
both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has
been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed
(Fast_Read), Dual Output Fast Read (3Bh), Dual I/O Fast Read (BBh), Quad Input/Output
FAST_READ (EBh), Read Status Register (RDSR), Read Suspend Status Register (RDSSR) or
Release from Deep Power-down, and Read Device ID (RDI) instruction, the shifted-in instruction se-
quence is followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the
data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Half Block Erase (HBE), Block Erase (BE),
Chip Erase (CE), Write Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep
Power-down (DP) instruction, Chip Select (CS#) must be driven High exactly at a byte boundary,
otherwise the instruction is rejected, and is not executed. That is, Chip Select (CS#) must driven High
when the number of clock pulses after Chip Select (CS#) being driven Low is an exact multiple of eight.
For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not
be reset.
In the case of multi-byte commands of Page Program (PP), Quad Input Page Program (QPP) and
Release from Deep Power Down (RES ) minimum number of bytes specified has to be given,
without which, the command will be ignored.
In the case of Page Program, if the number of byte after the command is less than 4 (at least 1
data byte), it will be ignored too. In the case of SE, HBE and BE, exact 24-bit address is a must,
any less or more will cause the command to be ignored.
All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase
cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues
unaffected.


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