EN25S20A datasheet(39/65 Pages) EON

Part #	EN25S20A

Description	2 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector

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Manufacturer	EON [Eon Silicon Solution Inc.]

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39

EN25S20A

Rev. A, Issue Date: 2014/01/16

Sector Erase (SE) (20h)

The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be

accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write

Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).

The Sector Erase (SE) instruction is entered by driving Chip Select (CS#) Low, followed by the in-

struction code, and three address bytes on Serial Data Input (DI). Any address inside the Sector (see

Table 2) is a valid address for the Sector Erase (SE) instruction. Chip Select (CS#) must be driven Low

for the entire duration of the sequence.

The instruction sequence is shown in Figure 27. Chip Select (CS#) must be driven High after the eighth

bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not

executed. As soon as Chip Select (CS#) is driven High, the self-timed Sector Erase cycle (whose du-

ration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read

to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the

self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle

is completed, the Write Enable Latch (WEL) bit is reset.

A Sector Erase (SE) instruction applied to a sector which is protected by the Block Protect (BP3, BP2,

BP1, BP0) bits (see Table 3) is not executed.

The instruction sequence is shown in Figure 29.1 while using the Enable Quad Peripheral Interface

mode (EQPI) (38h) command.

Figure 27. Sector Erase Instruction Sequence Diagram

32KB Half Block Erase (HBE) (52h)

The Half Block Erase (HBE) instruction sets to 1 (FFh) all bits inside the chosen block. Before it can be

accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write

Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).

The Half Block Erase (HBE) instruction is entered by driving Chip Select (CS#) Low, followed by the in-

struction code, and three address bytes on Serial Data Input (DI). Any address inside the Block (see

Table 2) is a valid address for the Block Erase (BE) instruction. Chip Select (CS#) must be driven Low

for the entire duration of the sequence.

The instruction sequence is shown in Figure 28. Chip Select (CS#) must be driven High after the eighth

bit of the last address byte has been latched in, otherwise the Half Block Erase (HBE) instruction is not

executed. As soon as Chip Select (CS#) is driven High, the self-timed Half Block Erase cycle (whose

duration is tHBE) is initiated. While the Half Block Erase cycle is in progress, the Status Register may

be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1

during the self-timed Half Block Erase cycle, and is 0 when it is completed. At some unspecified time

before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

A Half Block Erase (HBE) instruction applied to a block which is protected by the Block Protect (BP3,

BP2, BP1, BP0) bits (see Table 3) is not executed.

The instruction sequence is shown in Figure 29.1 while using the Enable Quad Peripheral Interface mode

(EQPI) (38h) command.

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