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EN25S20A Datasheet(PDF) 18 Page - Eon Silicon Solution Inc.

Part No. EN25S20A
Description  2 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector
Download  65 Pages
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Maker  EON [Eon Silicon Solution Inc.]
Homepage  http://www.essi.com.tw

EN25S20A Datasheet(HTML) 18 Page - Eon Silicon Solution Inc.

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This Data Sheet may be revised by subsequent versions
©2014 Eon Silicon Solution, Inc.,
or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2014/01/16
against Page Program (PP) Sector Erase (SE), Half Block Erase (HBE) and Block Erase (BE),
instructions. The Block Protect (BP3, BP2, BP1, BP0) bits can be written and provided that the Hard-
ware Protected mode has not been set. The Chip Erase (CE) instruction is executed if, and only if, all
Block Protect (BP3, BP2, BP1, BP0) bits are 0.
WHDIS bit.
The WP# and Hold# Disable bit (WHDIS bit), non-volatile bit, it indicates the WP# and
HOLD# are enabled or not. When it is “0” (factory default), the WP# and HOLD# are enabled. On the
other hand, while WHDIS bit is “1”, the WP# and HOLD# are disabled. No matter WHDIS is “0" or
1", the system can executes Quad Input/Output FAST_READ (EBh) , Quad Input Page Program (32h)
or EQPI (38h) command directly. User can use Flash Programmer to set WHDIS bit as “1" and then
the host system can let WP# and HOLD# keep floating in SPI mode.
SRP bit / OTP_LOCK bit.
The Status Register Protect (SRP) bit is operated in conjunction with the
Write Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal
allow the device to be put in the Hardware Protected mode (when the Status Register Protect (SRP) bit
is set to 1, and Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status
Register (SRP, BP3, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR)
instruction is no longer accepted for execution.
In OTP mode, this bit is served as OTP_LOCK bit, user can read/program/erase OTP sector as normal
sector while OTP_LOCK value is equal 0, after OTP_LOCK is programmed with 1 by WRSR command,
the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only be
programmed once.
Note :
In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,
user must clear the protect bits before enter OTP mode and program the OTP code, then execute
WRSR command to lock the OTP sector before leaving OTP mode.
Read Suspend Status Register (RDSSR) (09h)
The Read Suspend Status Register (RDSSR) instruction allows the Suspend Status Register to be
read. The Suspend Status Register may be read at any time, even while a Write Suspend or Write
Resume cycle is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the
Suspend Status Register continuously, as shown in Figure 11.
The instruction sequence is shown in Figure 11.1 while using the Enable Quad Peripheral Interface
mode (EQPI) (38h) command.
Figure 11. Read Suspend Status Register Instruction Sequence Diagram

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