RNA52A10T_15 datasheet(5/12 Pages) RENESAS

Part #	RNA52A10T

Description	Dual CMOS system?밨ESET IC

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Manufacturer	RENESAS [Renesas Technology Corp]

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RNA52A10T

R03DS0078EJ0200 Rev.2.00

Page 5 of 11

Dec 19, 2015

Electrical Characteristics

(Ta = 25°C, unless otherwise noted)

Item

Symbol

Min.

Typ.

Max.

Unit

Test Conditions

Test

Circuit

Supply voltage

VDD

1.4

—

5.5

V

—

Current consumption

IDD

—

1.1

19

μA

VDD = 5.5 V

Vi1 = V i2 = 5.5 V

1

Reference voltage

VREF

0.95

1.00

1.05

V

VDD = 3.3 V

2

Reference voltage temperature

coefficient

(Reference value for design)

ΔVREF

VREF

⋅ΔTa

—

±100

—

ppm

°C

Ta = –40 to 85°C

2

Vi1, Vi2 input

hysteresis voltage

VHYS

28.5

(VREF

×3%)

60

(VREF

×6%)

94.5

(VREF

×9%)

mV

VDD = 3.3 V

2

Vi1, Vi2 input current

IIN

—

0.6

2.2

μA

VDD = 5.5 V

Vi1 = V i2 = 5.5 V

3

CD input threshold voltage

VDLY

VDD

×0.43

VDD

×0.63

VDD

×0.83

V

VDD = 3.3 V

Vi1 = V i2 = 1.2 V

4

Vo1, Vo2

low-level output voltage

VOL

—

0.05

0.15

V

VDD = 1.4V

Vi1 = V i2 = 0 V

IOL = 0.5 mA

5

—

0.15

0.35

V

VDD = 3.3V

Vi1 = V i2 = 0 V

IOL = 5 mA

6

Vo1, Vo2

output leakage current

ILK

—

100

nA

VDD = VO1 = VO2 = 5.5 V

Vi1 = V i2 = 1.2 V

7

Vo2

Delay time

Note1

Incomplete

discharge of

capacity CD

TDLY

1.1

11

17

ms

VDD = 3.3 V

Vi2 = 0 V

→1.2 V

CD = 0.3

μF, RD = 39 kΩ

8

complete

discharge of

capacity CD

TDLY0

7

11

17

ms

8

Vo1

Rise response time

TPLH

—

30

300

μs

VDD = 3.3 V

Vi1 = 0 V

→1.2 V

9

Vo1, Vo2

fall response time

TPHL

—

30

800

μs

VDD = 3.3 V

Vi1 = Vi2 = 1.2 V

→0 V

CD = 0.3

μF, RD = 39 kΩ

10

MR low-level input voltage

VIL

—

VDD

×0.2

V

VDD = 3.3 V

Vi1 = V i2 = 1.2 V

11

MR high-level

input voltage

VDD < 4.5V

VIH

VDD

×0.75

—

V

VDD = 3.3 V

Vi1 = V i2 = 1.2 V

11

VDD

≥ 4.5V

VDD

×0.5

—

V

VDD = 5.0 V

Vi1 = V i2 = 1.2 V

12

MR input

pull-down resistance

RMR

0.5

2

—

M

Ω

VDD = 5.5 V

VMR = 5.5 V

13

Notes: 1. When capacitor CD is completely discharged and charging starts in the state that CD pin voltage is 0 V, the

minimum value of delay time TDLY0 is 7 ms. However, when the discharging time is short and charging starts

in the state that the voltage does not completely fall to 0 V, the minimum value of delay time TDLY is 1.1 ms.

Then, the minimum value of Low time (reset time) of

Vo2 is 1.1 ms as the delay time T

DLY. Refer to

Regulations for state of capacitor CD electrical discharge and delay time on page 10 for details.

2. Refer to the characteristic curves on page 6 for temperature dependence of the main characteristics.

3. Refer to pages 8 and 9 for the test circuits.

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