ADN2819_15 datasheet(13/24 Pages) AD | Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

13 / 24 page

ADN2819

Rev. B | Page 13 of 24

The gain of the loop integrator is small for high jitter

frequencies, so larger phase differences are needed to make the

loop control voltage big enough to tune the range of the phase

shifter. Large phase errors at high jitter frequencies cannot be

tolerated. In this region, the gain of the integrator determines

the jitter accommodation. Since the gain of the loop integrator

declines linearly with frequency, jitter accommodation is lower

with higher jitter frequency. At the highest frequencies, the loop

gain is very small and little tuning of the phase shifter can be

expected. In this case, jitter accommodation is determined by

the eye opening of the input data, the static phase error, and the

residual loop jitter generation. The jitter accommodation is

roughly 0.5 UI in this region. The corner frequency between the

declining slope and the flat region is the closed-loop bandwidth

of the delay-locked loop, which is roughly 5 MHz for OC-12,

OC-48, and GbE data rates, and 600 kHz for OC-3 data rates.

JITTER PEAKING

IN ORDINARY PLL

ADN2819

Z(s)

X(s)

f (kHz)

JITTER

GAIN

(dB)

n psh

d psh

Figure 16. Jitter Response vs. Conventional PLL

ADN2819 Datasheet(PDF) 13 Page - Analog Devices