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ADN2816 Datasheet(PDF) 20 Page  Analog Devices 

ADN2816 Datasheet(HTML) 20 Page  Analog Devices 
20 / 24 page ADN2816 Data Sheet Rev. C  Page 20 of 24 Transmission Lines Use of 50 Ω transmission lines is required for all high frequency input and output signals to minimize reflections: PIN, NIN, CLKOUTP, CLKOUTN, DATAOUTP, and DATAOUTN (also REFCLKP and REFCLKN, if a high frequency reference clock is used, such as 155 MHz). It is also necessary for the PIN/NIN input traces to be matched in length, and the CLKOUTP/ CLKOUTN and DATAOUTP/DATAOUTN output traces to be matched in length to avoid skew between the differential traces. The high speed inputs, PIN and NIN, are internally terminated with 50 Ω to an internal reference voltage (see Figure 20). A 0.1 μF is recommended between VREF, Pin 3, and GND to provide an ac ground for the inputs. As with any high speed mixedsignal design, take care to keep all high speed digital traces away from sensitive analog nodes. CIN CIN 50 0.1 F 50 3k NIN PIN ADN2816 2.5V VREF 50 50 TIA VCC Figure 20. ADN2816 ACCoupled Input Configuration Soldering Guidelines for Lead Frame Chip Scale Package The lands on the 32lead LFCSP are rectangular. The printed circuit board (PCB) pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a central exposed pad. The pad on the PCB should be at least as large as this exposed pad. The user must connect the exposed pad to VEE using plugged vias so that solder does not leak through the vias during reflow. This ensures a solid connection from the exposed pad to VEE. Choosing AC Coupling Capacitors AC coupling capacitors at the input (PIN, NIN) and output (DATAOUTP, DATAOUTN) of the ADN2816 must be chosen such that the device works properly over the full range of data rates used in the application. When choosing the capacitors, the time constant formed with the two 50 Ω resistors in the signal path must be considered. When a large number of consecutive identical digits (CIDs) are applied, the capacitor voltage can droop due to baseline wander (see Figure 21), causing pattern dependent jitter (PDJ). The user must determine how much droop is tolerable and choose an ac coupling capacitor based on that amount of droop. The amount of PDJ can then be approximated based on the capacitor selection. The actual capacitor value selection can require some tradeoffs between droop and PDJ. For example, assuming 2% droop can be tolerated, then the maximum differential droop is 4%. Normalizing to V pp: Droop = Δ V = 0.04 V = 0.5 V pp (1 − e–t/τ); therefore, τ = 12t where: τ is the RC time constant (C is the ac coupling capacitor, R = 100 Ω seen by C). t is the total discharge time, which is equal to nT. n is the number of CIDs. T is the bit period. The capacitor value can then be calculated by combining the equations for τ and t: C = 12 nT/R Once the capacitor value is selected, the PDJ can be approximated as 6. 0 / 1 5 . 0 r nT/RC pspp e t PDJ where: PDJpspp is the amount of patterndependent jitter allowed; < 0.01 UI pp typical. tr is the rise time, which is equal to 0.22/BW, where BW ~ 0.7 (bit rate). Note that this expression for tr is accurate only for the inputs. The output rise time for the ADN2816 is ~100 ps, regardless of data rate. 
