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ADN2816 Datasheet(PDF) 17 Page - Analog Devices
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ADN2816 Datasheet(HTML) 17 Page - Analog Devices
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Rev. C | Page 17 of 24
The user can specify a fixed integer multiple of the reference
clock to lock onto using CTRLA[5:2], where CTRLA should be
set to the data rate/DIV_F
, where DIV_F
divided-down reference referred to the 10 MHz to 20 MHz
band. For example, if the reference clock frequency is
38.88 MHz and the input data rate is 622.08 Mb/s, then
CTRLA[7:6] is set to  to give a divided-down reference
clock of 19.44 MHz. CTRLA[5:2] is set to , that is, 5,
622.08 Mb/s/19.44 MHz = 2
In this mode, if the ADN2816 loses lock for any reason, it
relocks onto the reference clock and continues to output a stable
While the ADN2816 is operating in lock-to-reference mode, if
the user ever changes the reference frequency, the F
(CTRLA[7:6]) or the F
ratio (CTRLA[5:2]), this must be
followed by writing a 0 to 1 transition into the CTRLA bit to
initiate a new lock-to-reference command.
Using the Reference Clock to Measure Data Frequency
The user can also provide a reference clock to measure the
recovered data frequency. In this case, the user provides a
reference clock, and the ADN2816 compares the frequency of
the incoming data to the incoming reference clock and returns a
ratio of the two frequencies to 0.01% (100 ppm). The accuracy
error of the reference clock is added to the accuracy of the
ADN2816 data rate measurement. For example, if a 100 ppm
accuracy reference clock is used, the total accuracy of the
measurement is within 200 ppm.
The reference clock can range from 10 MHz and 160 MHz. The
ADN2816 expects a reference clock between 10 MHz and
20 MHz by default. If it is between 20 MHz and 40 MHz,
40 MHz and 80 MHz, or 80 MHz and 160 MHz, the user needs
to configure the ADN2816 to use the correct reference
frequency range by setting two bits of the CTRLA register,
CTRLA[7:6]. Using the reference clock to determine the
frequency of the incoming data does not affect the manner in
which the part locks onto data. In this mode, the reference clock
is used only to determine the frequency of the data. For this
reason, the user does not need to know the data rate to use the
reference clock in this manner.
Prior to reading back the data rate using the reference clock, the
CTRLA[7:6] bits must be set to the appropriate frequency range
with respect to the reference clock being used. A fine data rate
readback is then executed as follows:
1. Write a 1 to CTRLA. This enables the fine data rate
measurement capability of the ADN2816. This bit is level
sensitive and does not need to be reset to perform subsequent
2. Reset MISC by writing a 1 followed by a 0 to CTRLB.
This initiates a new data rate measurement.
3. Read back MISC. If it is 0, the measurement is not
complete. If it is 1, the measurement is complete and the data
rate can be read back on FREQ[22:0]. The time for a data rate
measurement is typically 80 ms.
4. Read back the data rate from Registers FREQ2[6:0],
FREQ1[7:0], and FREQ0[7:0].
The data rate can be determined by
FREQ[22:0] is the reading from FREQ2[6:0] MSByte,
FREQ1[7:0], and FREQ0[7:0] LSByte.
is the data rate (Mb/s).
is the REFCLK frequency (MHz).
SEL_RATE is the setting from CTRLA[7:6].
For example, if the reference clock frequency is 32 MHz,
SEL_RATE = 1, since the CTRLA[7:6] setting is , because
the reference frequency falls into the 20 MHz to 40 MHz range.
Assume for this example that the input data rate is 622.08 Mb/s
(OC-12). After following Step 1 through Step 4, the value that is
read back on FREQ[22:0] = 0x9B851, which is equal to 637 × 10
Plugging this value into the equation yields
637e3 × 32e6/2
= 622.08 Mb/s
If subsequent frequency measurements are required, CTRLA
should remain set to 1. It does not need to be reset. The
measurement process is reset by writing a 1 followed by a 0 to
CTRLB. This initiates a new data rate measurement. Follow
Step 2 through Step 4 to read back the new data rate.
Note that a data rate readback is valid only if LOL is low. If LOL
is high, the data rate readback is invalid.
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