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ADMCF326 Datasheet(PDF) 12 Page - Analog Devices |
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ADMCF326 Datasheet(HTML) 12 Page - Analog Devices |
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12 / 36 page  ADMCF326 –12– REV. B A functional block diagram of the PWM controller is shown in Figure 6. The generation of the six output PWM signals on pins AH to CL is controlled by four important blocks: • The three-phase PWM timing unit, which is the core of the PWM controller, generates three pairs of complemented and dead-time-adjusted center-based PWM signals. • The output control unit allows the redirection of the outputs of the three-phase timing unit for each channel to either the high side or low side output. In addition, the output control unit allows individual enabling/disabling of each of the six PWM output signals. • The GATE drive unit provides the high chopping frequency and its subsequent mixing with the PWM signals. • The PWM shutdown controller manages the two PWM shut- down modes (via the PWMTRIP pin, and the PWMSWT Register) and generates the correct RESET signal for the Timing Unit. • The PWM controller is driven by a clock at the same frequency as the DSP instruction rate, CLKOUT, and is capable of generating two interrupts to the DSP core. One interrupt is generated on the occurrence of a PWMSYNC pulse, and the other is generated on the occurrence of any PWM shut- down action. Three-Phase Timing Unit The 16-bit three-phase timing unit is the core of the PWM con- troller and produces three pairs of pulsewidth modulated signals with high resolution and minimal processor overhead. There are four main configuration registers (PWMTM, PWMDT, PWMPD, and PWMSYNCWT) that determine the fundamental charac- teristics of the PWM outputs. In addition, the operating mode of the PWM (Single or Double Update Mode) is selected by Bit 6 of the MODECTRL Register. These registers, in conjunction with the three 16-bit duty cycle registers (PWMCHA, PWMCHB, and PWMCHC), control the output of the three-phase timing unit. PWM Switching Frequency: PWMTM Register The PWM switching frequency is controlled by the PWM period register, PWMTM. The fundamental timing unit of the PWM controller is tCK = 1/fCLKOUT, where fCLKOUT, is the CLKOUT frequency (DSP instruction rate). Therefore, for a 20 MHz CLKOUT, the fundamental time increment is 50 ns. The value written to the PWMTM Register is effectively the number of tCK clock increments in half a PWM period. The required PWMTM value is a function of the desired PWM switching frequency (fPWM) and is given by: PWMTM f f f f CLKOUT PWM CLKIN PWM = × = 2 Therefore, the PWM switching period, TS, can be written as: T PWMTM t SCK =× × 2 PWMTRIP OR PWMSWT (0) PWM SHUTDOWN CONTROLLER PWMTRIP PWMSEG (8...0) OUTPUT CONTROL UNIT GATE DRIVE UNIT CLK PWM DUTY CYCLE REGISTERS PWM CONFIGURATION REGISTERS TO INTERRUPT CONTROLLER THREE-PHASE PWM TIMING UNIT CLK RESET SYNC SYNC PWMSYNC CLKOUT AH AL BH BL CH CL PWMGATE (9...0) PWMTM (15...0) PWMDT (9...0) PWMPD (15...0) PWMSYNCWT (7...0) MODECTRL (6) PWMCHA (15...0) PWMCHB (15...0) PWMCHC (15...0) Figure 6. Overview of the PWM Controller of the ADMCF326 |
Similar Part No. - ADMCF326_15 |
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Similar Description - ADMCF326_15 |
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