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ADMC200 Datasheet(PDF) 2 Page - Analog Devices |
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ADMC200 Datasheet(HTML) 2 Page - Analog Devices |
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2 / 12 page  ADMC200–SPECIFICATIONS (VDD = +5 V 5%; AGND = DGND = 0 V; REFIN = 2.5 V; External Clock = 12.5 MHz; TA = –40 C to +85 C unless otherwise noted) Parameter ADMC200AP Units Conditions/Comments ANALOG-TO-DIGITAL CONVERTER 1 Resolution 11 Bits Twos Complement Data Format Relative Accuracy ± 2 LSB max Integral Nonlinearity Differential Nonlinearity ± 2 LSB max Bias Offset Error ± 5 LSB max Any Channel Bias Offset Match 4 LSB max Between Channels Full-Scale Error ± 6 LSB max Any Channel Full-Scale Error Match 4 LSB max Between Channels Conversion Time/Channel 40 System CLK Cycles Signal-to-Noise Ratio (SNR) 2 60 dB min fIN = 600 Hz Sine Wave, fSAMPLE = 55 kHz, 600 Hz Channel-to-Channel Isolation Sine Wave Applied to Unselected Channels Two-/Three-Phase Mode –58 dB max Three-/Three-Phase Mode –55 dB max ANALOG INPUTS Input Voltage Level 0–5 Volts Analog Input Current 100 µA max Input Capacitance 10 pF typ TRACK AND HOLD Aperture Delay 200 ns max Any Channel Aperture Time Delay Match 20 ns max Between Channels SHA Acquisition Time 20 System CLK Cycles Droop Rate 5 mV/ms max REFERENCE INPUT Voltage Level 2.5 V dc Reference Input Current 50 µA max REFERENCE OUTPUT Voltage Level 2.5 Volts Voltage Level Tolerance ± 5 % max Full Load Drive Capability ±200 µA max LOGIC VIL 0.8 V max VIH 2.0 V min VOL 0.4 V max ISINK = 400 µA, V DD = 5 V VOH 4.5 V min ISOURCE = 20 µA, V DD = 5 V Input Leakage Current 1 µA max Three-State Leakage Current 1 µA max Input Capacitance 20 pF typ PWM TIMERS Resolution 12 Bits Programmable Deadtime Range 0–10.08 µs Programmable Deadtime Increments 2 System CLK Cycles 160 ns Programmable Pulse Deletion Range 0–10.16 µs Programmable Deletion Increments 1 System CLK Cycle 80 ns Minimum PWM Frequency 1.5 kHz Resolution Varies with PWM Switching Frequency (10 MHz Clock: 20 kHz = 9 Bits, 10 kHz = 10 Bits, 5 kHz = 11 Bits, 2.5 kHz = 12 Bits). Higher Fre- quencies are Available with Lower Resolution VECTOR TRANSFORMATION Park & Clarke Transformation Radius Error 0.7 % max Angular Error 30 arc min max Reverse Transformation Time 37 System CLK Cycles Forward Transformation Time 40 System CLK Cycles EXTERNAL CLOCK INPUT Range 6.25–25 MHz If > 12.5 MHz, Then It Is Necessary to Divide Down via SYSCTRL Register INTERNAL SYSTEM CLOCK Range 6.25–12.5 MHz POWER SUPPLY CURRENT IDD 20 mA max NOTES 1Measurements made with external reference. 2Tested with PWM Switching Frequency of 25 kHz. Specifications subject to change without notice. REV. B –2– |
Similar Part No. - ADMC200_15 |
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Similar Description - ADMC200_15 |
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