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ADM8692 Datasheet(PDF) 17 Page - Analog Devices

Part No. ADM8692
Description  Microprocessor Supervisory Circuits
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ADM8692 Datasheet(HTML) 17 Page - Analog Devices

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Rev. B | Page 17 of 20
(200 ms for the ADM8695) to allow for this oscillator start-up
time. If a different reset pulse width is required, a capacitor
should be connected to OSC IN, or an external clock can be
used. Refer to Table 5 and Figure 17, Figure 18, Figure 19, and
Figure 20. The manual reset switch and the 0.1 µF capacitor
connected to the reset line can be omitted if a manual reset is
not needed. An inverted, active high, RESET output is also
The 5 V VCC power line is monitored via a resistive potential
divider connected to the power-fail input (PFI). When the
voltage at PFI falls below 1.3 V, the power-fail output (PFO)
drives the processor’s NMI input low. If, for example, a power-
fail threshold of 4.8 V is set with Resistor R1 and Resistor R2, the
microprocessor has the time when VCC falls from 4.8 V to 4.65 V
to save data into RAM. An earlier power-fail warning can be
generated if the unregulated dc input to the 5 V regulator is
available for monitoring. This allows more time for microprocessor
housekeeping tasks to be completed before power is lost.
The ADM8691/ADM8693/ADM8695 CEOUT line drives the
chip select inputs of the CMOS RAM. CEOUT follows CEIN as
long as VCC is above the 4.65 V (4.4 V for the ADM8693) reset
If VCC falls below the reset threshold, CEOUT goes high,
independent of the logic level at CEIN. This prevents the
microprocessor from writing erroneous data into RAM during
power-up, power-down, brownouts, and momentary power
The microprocessor drives the watchdog input (WDI) with an
input/output line. When OSC IN and OSC SEL are unconnected,
the microprocessor must toggle the WDI pin once every
1.6 seconds to verify proper software execution. If a hardware
or software failure occurs such that WDI is not toggled, the
ADM8691/ADM8693 issues a 50 ms (200 ms for the ADM8695)
RESET pulse after 1.6 seconds. This typically restarts the micro-
processor power-up routine. A new RESET pulse is issued every
1.6 seconds until WDI is again strobed. If a different watchdog
timeout period is required, a capacitor should be connected to
OSC IN or an external clock can be used. Refer to Table 5 and
Figure 17, Figure 18, Figure 19, and Figure 20.
The watchdog output (WDO) goes low if the watchdog timer is
not serviced within its timeout period. Once WDO goes low, it
remains low until a transition occurs at WDI. The watchdog
timer feature can be disabled by leaving WDI unconnected.
The RESET output has an internal 3 µA pull-up and can either
connect to an open collector reset bus or directly drive a CMOS
gate without an external pull-up resistor.

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