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ICL8068ACDD Datasheet(PDF) 3 Page - Intersil Corporation |
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ICL8068ACDD Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 21 page 5-8 Pin Descriptions PIN NO. SYMBOL OPTION DESCRIPTION 1 V++ Positive Supply Voltage: Nominally +15V. 2 GND Digital Ground: 0V, ground return. 3 STTS Status Output: HI during integrate and deintegrate until data is latched. LO when analog section is in auto-zero configuration. 4 POL Polarity: Three-state output. HI for positive input. 5 OR Over Range: Three-state output. 6 BIT 16 BIT 14 -16 -14 Most Significant Bit (MSB). 7 BIT 15 BIT 13 -16 -14 DATA Bits: Three-state outputs. See Table 3 for format of ENABLES and bytes. HIGH = true. 8 BIT 14 BIT 12 -16 -14 9 BIT 13 BIT 11 -16 -14 10 BIT 12 BIT 10 -16 -14 11 BIT 11 BIT 9 -16 -14 12 BIT 10 NC -16 -14 13 BIT 9 NC -16 -14 14 BIT 8 15 BIT 7 16 BIT 6 17 BIT 5 18 BIT 4 19 BIT 3 20 BIT 2 21 BIT 1 Least Significant Bit (LSB). 22 LBEN LOW BYTE ENABLE: If not in handshake mode (see pin 27) when LO (with CE/LD, pin 30) activates low-order byte outputs, BITS 1-8. When in handshake mode (see pin 27), serves as a low byte flag output. See Figures 11, 12, 13. 23 MBEN -16 MID BYTE ENABLE: Activates Bits 9-16, see LBEN (pin 22) HBEN -14 HIGH BYTE ENABLE: Activates Bits 9-14, POL, OR, see LBEN (pin 22) 24 HBEN -16 HIGH BYTE ENABLE: Activates POL, OR, see LBEN (pin 22). CLOCK3 -14 RC oscillator pin: Can be used as clock output. ICL8052/ICL7104, ICL8068/ICL7104 |
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