6

FN3093.3

Digital Section

Figure 5 shows the Digital Section of the ICL7135. The

ICL7135 includes several pins which allow it to operate

conveniently in more sophisticated systems. These include:

Run/HOLD (Pin 25)

When high (or open) the A/D will free-run with equally

spaced measurement cycles every 40,002 clock pulses. If

taken low, the converter will continue the full measurement

cycle that it is doing and then hold this reading as long as

R/H is held low. A short positive pulse (greater than 300ns)

will now initiate a new measurement cycle, beginning with

between 1 and 10,001 counts of auto zero. If the pulse

occurs before the full measurement cycle (40,002 counts) is

completed, it will not be recognized and the converter will

simply complete the measurement it is doing. An external

indication that a full measurement cycle has been completed

is that the first strobe pulse (see below) will occur 101 counts

after the end of this cycle. Thus, if Run/HOLD is low and has

been low for at least 101 counts, the converter is holding and

ready to start a new measurement when pulsed high.

STROBE (Pin 26)

This is a negative going output pulse that aids in transferring

the BCD data to external latches, UARTs, or

microprocessors. There are 5 negative going STROBE

pulses that occur in the center of each of the digit drive

pulses and occur once and only once for each measurement

cycle starting 101 clock pulses after the end of the full

measurement cycle. Digit 5 (MSD) goes high at the end of

the measurement cycle and stays on for 201 counts. In the

center of this digit pulse (to avoid race conditions between

changing BCD and digit drives) the first STROBE pulse goes

4 goes high (for 200 clock pulses) and 100 pulses later the

STROBE goes negative for the second time. This continues

through digit 1 (LSD) when the fifth and last STROBE pulse

is sent. The digit drive will continue to scan (unless the

previous signal was overrange) but no additional STROBE

pulses will be sent until a new measurement is available.

BUSY (Pin 21)

BUSY goes high at the beginning of signal integrate and

stays high until the first clock pulse after zero crossing (or

after end of measurement in the case of an overrange). The

internal latches are enabled (i.e., loaded) during the first

clock pulse after busy and are latched at the end of this clock

pulse. The circuit automatically reverts to auto-zero when not

BUSY, so it may also be considered a (Zl + AZ) signal. A

very simple means for transmitting the data down a single

wire pair from a remote location would be to AND BUSY with

clock and subtract 10,001 counts from the number of pulses

received - as mentioned previously there is one “NO-count”

pulse in each reference integrate cycle.

OVERRANGE (Pin 27)

This pin goes positive when the input signal exceeds the

range (20,000) of the converter. The output F/F is set at the

end of BUSY and is reset to zero at the beginning of

reference integrate in the next measurement cycle.

UNDERRANGE (Pin 28)

This pin goes positive when the reading is 9% of range or

less. The output F/F is set at the end of BUSY (if the new

reading is 1800 or less) and is reset at the beginning of

signal integrate of the next reading.

POLARlTY (Pin 23)

This pin is positive for a positive input signal. It is valid even

for a zero reading. In other words, +0000 means the signal is

positive but less than the least significant bit. The converter

can be used as a null detector by forcing equal frequency of

(+) and (-) readings. The null at this point should be less than

0.1 LSB. This output becomes valid at the beginning of

reference integrate and remains correct until it is revalidated

for the next measurement.

DIGITAL

CLOCK

RUN/

BUSY

OVER

STROBE

UNDER

MULTIPLEXER

ANALOG

GND

IN

HOLD

RANGE

RANGE

SECTION

MSB

LSB

CONTROL LOGIC

COUNTERS

ZERO

CROSS.

DET.

POLARITY

FF

LATCH

LATCH

LATCH

LATCH

LATCH

11

23

12

17

18

19

20

24

22

27

25

28

26

21

13

14

15

16

D1

D2

D3

D4

B1

B2

B4

B8

D5

FIGURE 5. DIGITAL SECTION OF THE ICL7135

ICL7135