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ICL7129 Datasheet(PDF) 5 Page - Intersil Corporation |
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ICL7129 Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 11 page 3-35 Detailed Description The ICL7129 is a uniquely designed single chip A/D converter. It features a new “successive integration” technique to achieve 10 µV resolution on a 200mV full-scale range. To achieve this resolution a 10:1 improvement in noise performance over previous monolithic CMOS A/D converters was accomplished. Previous integrating converters used an external capacitor to store an offset correction voltage. This technique worked well but greatly increased the equivalent noise bandwidth of the converter. The ICL7129 removes this source of error (noise) by not using an auto-zero capacitor. Offsets are cancelled using digital techniques instead. Savings in external parts cost are realized as well as improved noise performance and elimination of a source of electromagnetic and electrostatic pick-up. In the overall Functional Block Diagram of the ICL7129 the heart of this A/D converter is the sequence counter/decoder which drives the control logic and keeps track of the many separate phases required for each conversion cycle. The sequence counter is constantly running and is a separate counter from the up/down results counter which is activated only when the integrator is de-integrating. At the end of a con- version the data remaining in the results counter is latched, decoded and multiplexed to the liquid crystal display. The analog section block diagram shown in Figure 1 includes all of the analog switches used to configure the volt- age sources and amplifiers in the different phases of the cycle. The input and reference switching schemes are very similar to those in other less accurate integrating A/D con- verters. There are 5 basic configurations used in the full con- version cycle. Figure 2 illustrates a typical waveform on the integrator output. INT, INT1, and INT2 all refer to the signal integrate phase where the input voltage is applied to the integrator amplifier via the buffer amplifier. In this phase, the integrator ramps over a fixed period of time in a direction opposite to the polarity of the input voltage. DE1, DE2, and DE3 are the de-integrate phases where the reference capacitor is switched in series with the buffer ampli- fier and the integrator ramps back down to the level it started from before integrating. However, since the de-integrate phase can terminate only at a clock pulse transition, there is always a small overshoot of the integrator past the starting point. The ICL7129 amplifies this overshoot by 10 and DE2 begins. Simi- larly DE2’s overshoot is amplified by 10 and DE3 begins. At the end of DE3 the results counter holds a number with 5 1/ 2 digits of resolution. This was obtained by feeding counts into the results counter at the 31/2 digit level during DE1, into the 4 1/ 2 digit level during DE2 and the 5 1/ 2 digit level for DE3. The effects of offset in the buffer, integrator, and comparator can now be cancelled by repeating this entire sequence with the inputs shorted and subtracting the results from the original reading. For this phase INT2 switch is closed to give the same common-mode voltage as the measurement cycle. This assures excellent CMRR. At the end of the cycle the data in the up/down results counter is accurate to 0.02% of full scale and is sent to the display driver for decoding and multiplexing. FIGURE 1. ANALOG BLOCK DIAGRAM FIGURE 2. INTEGRATOR WAVEFORM FOR NEGATIVE INPUT VOLTAGE SHOWING SUCCESSIVE INTEGRATION PHASES AND RESIDUE VOLTAGE + - + - + - + - COMPARATOR 1 COMPARATOR 2 INTEGRATOR 100 10 X10 BUFFER REST, INT2 INT1, INT2 BUFFER REF HI REF LO INT, IN INT OUT IN HI COMMON IN LO INT TO DIGITAL SECTION Z1, X10 DE DE INT1 CINT RINT CREF DE+ DE- DE- DE+ REST X10 DE2 REST X10 DE3 DE1 DE-INTEGRATE ZERO-INTEGRATE INT1 INTEGRATE ZERO-INTEGRATE AND LATCH INTEGRATOR RESIDUE VOLTAGE 2000 CLOCKS 1000 CLOCKS 10,000 CLOCKS NOTE: Shaded area greatly expanded in time and amplitude. 1000 CLOCKS ICL7129 |
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