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ADM1485 Datasheet(PDF) 2 Page - Analog Devices

Part No. ADM1485
Description  5 V Low Power EIA RS-485 Transceiver
Download  11 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADM1485 Datasheet(HTML) 2 Page - Analog Devices

 
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REV.
–2–
ADM1485–SPECIFICATIONS (V
CC = 5 V
5%. All specifications TMIN to TMAX, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit Test Conditions/Comments
DRIVER
Differential Output Voltage, VOD
5.0
V
R =
∞, Test Circuit 1
2.0
5.0
V
VCC = 5 V, R = 50
Ω (RS-422), Test Circuit 1
1.5
5.0
V
R = 27
Ω (RS-485), Test Circuit 1
VOD3
1.5
5.0
V
VTST = –7 V to +12 V, Test Circuit 2
Δ|V
OD| for Complementary Output States
0.2
V
R = 27
Ω or 50 Ω, Test Circuit 1
Common-Mode Output Voltage VOC
3
V
R = 27
Ω or 50 Ω, Test Circuit 1
Δ|VOD| for Complementary Output States
0.2
V
R = 27
Ω or 50 Ω
Output Short-Circuit Current (VOUT = High)
35
250
mA
–7 V
≤ V
O
≤ +12 V
Output Short-Circuit Current (VOUT = Low)
35
250
mA
–7 V
≤ VO ≤ +12 V
CMOS Input Logic Threshold Low, VINL
0.8
V
CMOS Input Logic Threshold High, VINH
2.0
V
Logic Input Current (DE, DI)
±1.0
μA
RECEIVER
Differential Input Threshold Voltage, VTH
–0.2
+0.2
V
–7 V
≤ VCM ≤ +12 V
Input Voltage Hysteresis,
ΔVTH
70
mV
VCM = 0 V
Input Resistance
12
k
Ω
–7 V
≤ V
CM
≤ +12 V
Input Current (A, B)
1
mA
VIN = +12 V
–0.8
mA
VIN = –7 V
CMOS Input Logic Threshold Low, VINL
0.8
V
CMOS Input Logic Threshold High, VINH
2.0
V
Logic Enable Input Current (
RE)
±1
μA
CMOS Output Voltage Low, VOL
0.4
V
IOUT = +4.0 mA
CMOS Output Voltage High, VOH
4.0
V
IOUT = –4.0 mA
Short-Circuit Output Current
7
85
mA
VOUT = GND or VCC
Three-State Output Leakage Current
±1.0
μA
0.4 V
≤ V
OUT
≤ 2.4 V
POWER SUPPLY CURRENT
ICC (Outputs Enabled)
1.0
2.2
mA
Digital Inputs = GND or VCC
ICC (Outputs Disabled)
0.6
1
mA
Digital Inputs = GND or VCC
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Parameter
Min
Typ
Max
Unit Test Conditions/Comments
DRIVER
Propagation Delay Input to Output tPLH, tPHL
210
15
ns
RLDIFF = 54
Ω, C
L1 = CL2 = 100 pF, Test Circuit 3
Driver O/P to
O/P tSKEW
15
ns
RLDIFF = 54
Ω, CL1 = CL2 = 100 pF, Test Circuit 3
Driver Rise/Fall Time tR, tF
815
ns
RLDIFF = 54
Ω, CL1 = CL2 = 100 pF, Test Circuit 3
Driver Enable to Output Valid
10
25
ns
RL = 110
Ω, C
L = 50 pF, Test Circuit 4
Driver Disable Timing
10
25
ns
RL = 110
Ω, CL = 50 pF, Test Circuit 4
Matched Enable Switching
0
2
ns
RL = 110
Ω, CL = 50 pF, Test Circuit 4*
|tAZH –tBZL|, |tBZH –tAZL|
Matched Disable Switching
0
2
ns
RL = 110
Ω, CL = 50 pF, Test Circuit 4*
|tAHZ –tBLZ|, |tBHZ –tALZ|
RECEIVER
Propagation Delay Input to Output tPLH, tPHL
815
30
ns
CL = 15 pF, Test Circuit 5
Skew |tPLH –tPHL|5
ns
CL = 15 pF, Test Circuit 5
Receiver Enable tEN1
520
ns
CL = 15 pF, RL = 1 k
Ω, Test Circuit 6
Receiver Disable tEN2
520
ns
CL = 15 pF, RL = 1 k
Ω, Test Circuit 6
Tx Pulse Width Distortion
1
ns
Rx Pulse Width Distortion
1
ns
*Guaranteed by characterization.
Specifications subject to change without notice.
(VCC = 5 V
5%. All specifications TMIN to TMAX, unless otherwise noted.)


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