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W632GG6KB-11 Datasheet(PDF) 9 Page - Winbond |
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W632GG6KB-11 Datasheet(HTML) 9 Page - Winbond |
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9 / 159 page  W632GG6KB Publication Release Date: Dec. 08, 2014 Revision: A04 - 9 - 6. BALL DESCRIPTION BALL NUMBER SYMBOL TYPE DESCRIPTION J7, K7 CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. K9 CKE Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power Down and Self-Refresh operation (all banks idle), or Active Power Down (row Active in any bank). CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable during the power on and initialization sequence, they must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK#, ODT and CKE, are disabled during power down. Input buffers, excluding CKE, are disabled during Self-Refresh. L2 CS# Input Chip Select: All commands are masked when CS# is registered HIGH. CS# provides for external Rank selection on systems with multiple Ranks. CS# is considered part of the command code. K1 ODT Input On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is applied to each DQ, DQSU, DQSU#, DQSL, DQSL#, DMU, and DML signal. The ODT signal will be ignored if Mode Registers MR1 and MR2 are programmed to disable ODT and during Self Refresh. J3, K3, L3 RAS#, CAS#, WE# Input Command Inputs: RAS#, CAS# and WE# (along with CS#) define the command being entered. D3, E7 DMU, DML Input Input Data Mask: DMU and DML are the input mask signals control the lower or upper bytes for write data. Input data is masked when DMU/DML is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. M2, N8, M3 BA0 −BA2 Input Bank Address Inputs: BA0 −BA2 define to which bank an Active, Read, Write, or Precharge command is being applied. Bank address also determines which mode register is to be accessed during a MRS cycle. N3, P7, P3, N2, P8, P2, R8, R2, T8, R3, L7, R7, N7, T3 A0−A13 Input Address Inputs: Provide the row address for Active commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. (A10/AP and A12/BC# have additional functions; see below). The address inputs also provide the op-code during Mode Register Set command. Row address: A0 −A13. Column address: A0−A9. L7 A10/AP Input Auto-precharge: A10 is sampled during Read/Write commands to determine whether Auto-precharge should be performed to the accessed bank after the Read/Write operation. (HIGH: Auto-precharge; LOW: no Auto-precharge). A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses. N7 A12/BC# Input Burst Chop: A12/BC# is sampled during Read and Write commands to determine if burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See section 9.1 “Command Truth Table” on page 94 for details. T2 RESET# Input Active Low Asynchronous Reset: Reset is active when RESET# is LOW, and inactive when RESET# is HIGH. RESET# must be HIGH during normal operation. RESET# is a CMOS rai to rail signal with DC high and low at 80% and 20% of VDD, RESET# active is destructive to data contents. |
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