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ADM1041A Datasheet(PDF) 31 Page - Analog Devices |
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ADM1041A Datasheet(HTML) 31 Page - Analog Devices |
31 / 56 page ADM1041A Rev. 0 | Page 31 of 56 GENERAL SMBus TIMING The SMBus specification defines specific conditions for different types of read and write operations. General SMBus read and write operations are shown in the timing diagrams of Figure 25, Figure 26, and Figure 27, and described in the following sections. The general SMBus protocol operates as follows. The master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line, SDA, while the serial clock line, SCL, remains high. This indicates that a data stream follows. All slave peripherals connected to the serial bus respond to the start condition and shift in the next 8 bits, consisting of a 7-bit slave address (MSB first), plus an R/W bit, which determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read). The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowledge bit, and holding it low during the high period of this clock pulse. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, then the master writes to the slave device. If the R/W bit is a 1, the master reads from the slave device. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data, followed by an Acknowledge bit from the slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high may be interpreted as a stop signal. If the operation is a write operation, the first data byte after the slave address is a command byte. This tells the slave device what to expect next. It may be an instruction, such as telling the slave device to expect a block write, or it may be a register address that tells the slave where subsequent data is to be written. Because data can flow in only one direction as defined by the R/W bit, it is not possible to send a command to a slave device during a read operation. Before doing a read operation, it might first be necessary to perform a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the SDA line high during the tenth clock pulse to assert a stop condition. In read mode, the master device releases the SDA line during the low period before the ninth clock pulse, but the slave device does not pull it low. This is known as No Acknowledge. The master then takes the data line low during the low period before the tenth clock pulse, then high during the tenth clock pulse to assert a stop condition. Note: If it is required to perform several read or write operations in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation. START BY MASTER STOP BY MASTER ACK. BY ADM1041A ACK. BY ADM1041A ACK. BY ADM1041A A6 19 1 9 9 A5 A4 A3 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 SCLK SDATA FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE FRAME 3 DATA BYTE SDATA (CONTINUED) SCLK (CONTINUED) 9 1 D7 D6 D5 D4 D3 D2 D1 D0 Figure 25. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register |
Similar Part No. - ADM1041A_15 |
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Similar Description - ADM1041A_15 |
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