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HS-RTX2010 Datasheet(PDF) 8 Page - Intersil Corporation |
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HS-RTX2010 Datasheet(HTML) 8 Page - Intersil Corporation |
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8 / 36 page  8 NOTES: 11. Events in an interrupt sequence are as follows: e1. The Interrupt Controller samples the interrupt request inputs on the rising edge of PCLK. If NMI rises between e1 and the rising edge of PCLK prior to e5, the interrupt vector will be for NMI. e2. If any interrupt requests were sampled, the Interrupt Controller issues an interrupt request to the core on the falling edge of PCLK. e3. The core samples the state of the interrupt requests from the Interrupt Controller on the falling edge of PCLK. If INTSUP is high, maskable interrupts will not be detected at this time. e4. When the core samples an interrupt request on the falling edge of PCLK, an Interrupt Acknowledge cycle will begin on the next rising edge of PCLK. e5. Following the detection of an interrupt request by the core, an Interrupt Acknowledge cycle begins. The interrupt vector will be based on the highest priority interrupt request active at this time. 12. t44 is only required to determine when the Interrupt Acknowledge cycle will occur. 13. Interrupt requests should be held active until the Interrupt Acknowledge cycle for that interrupt occurs. FIGURE 6. INTERRUPT TIMING: WITH INTERRUPT SUPPRESSION FIGURE 7. INTERRUPT TIMING: WITH NO INTERRUPT SUPPRESSION Timing Diagrams (Continued) MA INTA INTSUP PCLK e1 e2 e3 e4 e5 t44 t46 t47 t46 t47 t67 t68 t28 t26 EI INT VECTOR e1 e2 e4 e5 t44 t46 t47 t67 t68 t26 t28 MA INTA INTSUP PCLK EI INT VECTOR HS-RTX2010RH |
Similar Part No. - HS-RTX2010 |
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