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5962R9676602VXC Datasheet(PDF) 11 Page - Intersil Corporation |
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5962R9676602VXC Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 14 page 11 HS-81C55RH, HS-81C56RH Input/Output Section The I/O section of the HS-81C55RH and HS-81C56RH consists of five registers: (See Figure 5) • Command/Status Register (C/S) - Both register are assigned the address XXXXX000. The C/S address serves the dual prupose. When the C/S registers are selected during WRITE operation, a command is written into the command register. The contents of this register are not accessible through the pins. When the C/S (XXXXX000) is selected during a READ operation, the status information of the I/O ports and the timer becomes available on the AD0 - AD7 lines. • PA Register - This register can be programmed to be either input or output ports depending on the status of the contents of the C/S Register. also depending on the command, this port can operate in either the basic mode or the strobed mode (See timing diagram). the I/O pins assigned in relation to this register are PA0 - PA7. The address of this register is XXXXX001. • PB Register - This register functions the same as PA Register. the I/O pins assigned are PB0 - PB7. The address of this register is XXXXX010 • PC Register - This register has the address XXXXX011 and contains only 6 bits. The 6 bits can be programmed to be either input ports, output ports or as control signals for PA and PB by properly programming the AD2 and AD3 bits of the C/S register. When PC0 - PC5 is used as a control port, 3 bits are assigned for Port A and 3 for Port B. The first bit is an Interrupt that the HS-81C55RH and HS-81C56RH sends out. The second is an output signal indicating whether the buffer is full or empty, and the third is an input pin to accept a strobe for the strobed input mode. (See Table 1). When the ‘C’ port is programmed to either ALT3 or ALT4, the control signals for PA and Pb are initialized as follows: : FIGURE 5. I/O PORT AND TIMER ADDRESSING SCHEME Figure 6 shows how I/O Ports A and B are structured within the HS-81C55RH and HS-81C56RH. Note in the diagram that when the I/O ports are programmed to be output ports, the contents of the output ports can still be read by a READ operation when appropriately addressed. CONTROL INPUT MODE OUTPUT MODE BF Low Low INTR Low High STB Input Control Input Control I/O ADDRESS† SELECTION A7 A6 A5 A4 A3 A2 A1 A0 XXXXX 0 0 0 Interval Command/ Status Register XXXXX 0 0 1 General Purpose I/O Port A XXXXX 0 1 0 General Purpose I/O Port B XXXXX 0 1 1 General Purpose I/O or Control Port C XXXXX 1 0 0 Low-Order 8 Bits of Timer Count XXXXX 1 0 1 High 6 Bits of Timer Count and 2 Bits of Timer Mode † I/O Address must be qualified by CE = 1(81C56RH) or CE = 0(81C55RH) and IO/M = 1 in order to select the appropriate register. X = Don’t Care FIGURE 6. HS-81C55RH AND HS-81C56RH PORT FUNCTION OUTPUT LATCH DQ CLK CLR D Q LATCH CLK STB (1) (2) (3) READ PORT MODE (4) WRITE PORT PA/PB PIN MUX HS-81C55RH AND HS-81C56RH ONE BIT OF PORT A OR PORT B (1) OUTPUT MODE (2) SIMPLE INPUT (3) STROBED INPUT (4) = 1 FOR OUTPUT MODE = 0 FOR INPUT MODE MULTIPLEXER CONTROL NOTES: 1. READ Port = (IO/M = 1)(RD = 0)(CE Active) (Port Address Selected) 2. WRITE Port = (IO/M = 1)(wr = 0)(CE Active) (Port Address Selected) Spec Number 518056 |
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