7

Specifications HS-80C85RH

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER

SYMBOL

(NOTE 1)

CONDITIONS

TEMPERATURE

LIMITS

UNITS

MIN

MAX

Input Capacitance

CIN

VDD = Open, f = 1MHz

-

12

pF

I/O Capacitance

CI/O

VDD = Open, f = 1MHz

-

13

pF

Output Capacitance

COUT

VDD = Open, f = 1MHz

-

12

pF

NOTE:

1. All measurements referenced to device ground.

TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS

NOTE:

The post irradiation test conditions and limits are the same as those listed in Tables 1 and 2.

TABLE 6. INTERRUPT PRIORITY, RESTART ADDRESS, AND SENSITIVITY

NAME

PRIORITY

ADDRESS BRANCHED TO (1)

WHEN INTERRUPT OCCURS

TYPE TRIGGER

TRAP

1

24H

Rising edge and high level until sampled.

RST 7.5

2

3CH

Rising edge (latched)

RST 6.5

3

34CH

High level until sampled.

RST 5.5

4

2CH

High level until sampled.

INTR

5

See Note 2

High level until sampled.

NOTES:

1. The processor pushes the PC on the stack before branching to the indicated address.

2. The address branched to depends on the instruction provided to the cpu when the interrupt is acknowledged.

SYMBOL

HS-8OC85RH

SYMBOL

HS-8OC85RH

tAL

(1/2)T- 175

Minimum

tCC

(3/2 + N)T - 175

Minimum

tLA

(1/2)T- 175

Minimum

tCL

(1/2)T - 190

Minimum

tLL

(1/2)T-50

Minimum

tARY

(3/2)T - 500

Maximum

tLCK

(1/2)T- 125

Minimum

tHACK

(1/2)T - 160

Minimum

tLC

(1/2)T- 100

Minimum

tHABF

(1/2)T +125

Maximum

tAD

(5/2 + N)T - 375

Maximum

tHABE

(1/2)T +125

Maximum

tRD

(3/2 + N)T - 375

Maximum

tAC

(2/2)T - 200

Minimum

tRAE

(1/2)T- 130

Minimum

t1

(1/2)T-210

Minimum

tCA

(1/2)T - 100

Minimum

t2

(1/2)T- 150

Minimum

tDW

(3/2 + N)T - 175

Minimum

tRV

(3/2)T - 200

Minimum

tWD

(1/2)T-100

Minimum

tLDR

(4/2)T - 325

Maximum

NOTE: N is equal to the total WAIT states T = tCYC

Spec Number

518054