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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

HS-80C85RH

Radiation Hardened

8-Bit CMOS Microprocessor

Description

The HS-80C85RH is an 8-bit CMOS microprocessor fabri-

cated using the Intersil radiation hardened self-aligned junc-

tion isolated (SAJI) silicon gate technology. Latch-up free

operation is achieved by the use of epitaxial starting material

to eliminate the parasitic SCR effect seen in conventional

bulk CMOS devices.

The HS-80C85RH is a functional logic emulation of the

HMOS 8085 and its instruction set is 100% software com-

patible with the HMOS device. The HS80C85RH is designed

for operation with a single 5 volt power supply. Its high level

of integration allows the construction of a radiation hardened

microcomputer system with as few as three ICs (HS-

80C85RH CPU, HS83C55RH ROM I/O, and the HS-81C55/

56RH RAM I/O.

Features

• Devices QML Qualified in Accordance With

MIL-PRF-38535

• Detailed Electrical and Screening Requirements are

Contained in SMD# 5962-95824 and Intersil’ QM Plan

• Radiation Hardened EPI-CMOS

• Low Standby Current 500

µA Max

• Electrically Equivalent to Sandia SA 3000

• 100% Software Compatible with INTEL 8085

• Operation from DC to 2MHz, Post Radiation

• Single 5 Volt Power Supply

• On-Chip Clock Generator and System Controller

• Four Vectored Interrupt Inputs

• Completely Static Design

• Self Aligned Junction Isolated (SAJI) Process

February 1996

Spec Number

518054

File Number

3036.2

Pinouts

40 LEAD CERAMIC DUAL-IN-LINE

METAL SEAL PACKAGE (SBDIP)

MIL-STD-1835, CDIP2-T40

TOP VIEW

42 LEAD CERAMIC METAL SEAL

FLATPACK PACKAGE (FLATPACK)

INTERSIL OUTLINE K42.A

TOP VIEW

33

34

35

36

37

38

39

40

32

31

30

29

24

25

26

27

28

21

22

23

HLDA

HOLD

READY

RD

IO / M

ALE

WR

VDD

S1

S0

A15

A14

A13

A12

A11

A10

A9

A8

13

1

2

3

4

5

6

7

8

9

10

11

12

14

15

16

17

18

19

20

INTR

INTA

SOD

SID

TRAP

RST 7.5

RST 6.5

RST 5.5

GND

X1

X2

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

RESET OUT

RESET IN

CLOCK OUT

HLDA

HOLD

READY

RD

IO / M

ALE

WR

VDD

S1

S0

A15

A14

A13

A12

A11

A10

A9

A8

RESET

CLOCK

GND

OUT

IN

INTR

INTA

SOD

SID

TRAP

RST 7.5

RST 6.5

RST 5.5

X1

X2

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

RESET

OUT

NC

NC

33

32

39

38

37

36

35

34

42

41

31

30

29

28

27

24

23

22

40

26

25

10

11

4

5

6

7

8

9

1

2

12

13

14

15

16

19

20

21

3

17

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