5962-8688001XA datasheet(10/15 Pages) INTERSIL

Part #	5962-8688001XA

Description	CMOS ARINC Bus Interface Circuit

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Manufacturer	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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10 / 15 page

5-192

AC Electrical Performance Speciﬁcations VDD = 5V ±5%, TA = 0oC to +70oC (HS-3282-5),

TA = -55

oC to +125oC (HS-3282-8)

PARAMETER

SYMBOL

CONDITIONS

LIMITS

UNITS

MIN

MAX

Clock Frequency

FC

VDD = 4.75V, 5.25V

-

1

MHz

Data Rate 1/

FD

VDD = 4.75V, 5.25V

-

100

kHz

Data Rate 2/

FD

VDD = 4.75V, 5.25V

-

12.5

kHz

Master Reset Pulse Width

TMR

VDD = 4.75V, 5.25V

200

-

ns

RECEIVER TIMING

Receiver Ready Time From 32nd Bit 1/

TD/R2

VDD = 4.75V, 5.25V

-

16

µs

Receiver Ready Time From 32nd Bit 2/

TD/R2

VDD = 4.75V, 5.25V

-

128

µs

Device Ready to Enable Time

TD/REN

VDD = 4.75V, 5.25V

0

-

ns

Data Enable Pulse Width

TEN

VDD = 4.75V, 5.25V

200

-

ns

Data Enable to Data Enable Time

TENEN

VDD = 4.75V, 5.25V

50

-

ns

Data Enable to Device Ready Reset Time

TEND/R

VDD = 4.75V, 5.25V

-

200

ns

Output Data Valid to Enable Time

TENDATA

VDD = 4.75V, 5.25V

-

200

ns

Data Enable to Data Select Time

TENSEL

VDD = 4.75V, 5.25V

20

-

ns

Data Select to Data Enable Time

TSELEN

VDD = 4.75V, 5.25V

20

-

ns

Output Data Disable Time

TDATAEN

VDD = 4.75V, 5.25V

-

80

ns

CONTROL WORD TIMING

Control Word Strobe Pulse Width

TCWSTR

VDD = 4.75V, 5.25V

130

-

ns

Control Word Setup Time

TCWSET

VDD = 4.75V, 5.25V

130

-

ns

Control Word Hold Time

TCWHLD

VDD = 4.75V, 5.25V

0

-

ns

TRANSMITTER FIFO Write Timing

Parallel Load Pulse Width

TPL

VDD = 4.75V, 5.25V

200

-

ns

Parallel Load to Parallel Load 2 Delay

TPL12

VDD = 4.75V, 5.25V

0

-

ns

Transmitter Ready Delay Time

TTX/R

VDD = 4.75V, 5.25V

-

840

ns

Data Word Setup Time

TDWSET

VDD = 4.75V, 5.25V

110

-

ns

Data Word Hold Time

TDWHLD

VDD = 4.75V, 5.25V

0

-

ns

TRANSMITTER Output Timing

Enable Transmit to Output Data Valid Time 1/

TENDAT

VDD = 4.75V, 5.25V

-

25

µs

Enable Transmit to Output Data Valid Time 2/

TENDAT

VDD = 4.75V, 5.25V

-

200

µs

Output Data Bit Time 1/

TBlT

VDD = 4.75V, 5.25V

4.95

5.05

µs

Output Data Bit Time 2/

TBlT

VDD = 4.75V, 5.25V

39.6

40.4

µs

Output Data Null Time 1/

TNULL

VDD = 4.75V, 5.25V

4.95

5.05

µs

Output Data Null Time 2/

TNULL

VDD = 4.75V, 5.25V

39.6

40.4

µs

HS-3282

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